Patent application number | Description | Published |
20100199253 | Routing Method for Double Patterning Design - A method of designing a double patterning mask set includes dividing a chip into a grid comprising grid cells; and laying out a metal layer of the chip. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first one of a first indicator and a second indicator, and all right-boundary patterns of the metal layer are assigned with a second one of the first indicator and the second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set, with all patterns assigned with the first indicator transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set. | 08-05-2010 |
20100205577 | Design Methods for E-Beam Direct Write Lithography - A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system. | 08-12-2010 |
20150079774 | Self-Alignment for using Two or More Layers and Methods of Forming Same - Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material. | 03-19-2015 |
Patent application number | Description | Published |
20080272378 | METHOD FOR FORMING A NITRIDE SEMICONDUCTOR LAYER AND METHOD FOR SEPARATING THE NITRIDE SEMICONDUCTOR LAYER FROM THE SUBSTRATE - There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point. | 11-06-2008 |
20080305571 | METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE SUBSTRATE - A method of fabricating a substrate for semiconductor light emitting devices is provided. The method includes forming a nanocrystal structure on a surface of the substrate which is a single crystal material, wherein the nanocrystal structure has an etched region and an unetched region. Next, a nitride semiconductor material is grown on the surface of the single crystal material with an epitaxial process, so as to form a substrate. Due to the periodicity of the nanocrystal structure, the semiconductor material grown on the substrate has fewer defects, and the material stress is reduced. Besides, the nanocrystal structure is capable of diffracting an electromagnetic wave, such that a higher light emitting efficiency and a higher output power may be obtained accordingly. | 12-11-2008 |
20090135593 | ASSEMBLY OF LIGHTING PANEL MODULES AND MANUFACTURING METHOD THEREOF - An assembly of lighting panel modules comprises a plurality of lighting panel modules and adhesive compound between the plurality of lighting panel modules. Each of the lighting panel modules comprises a light guide plate and at least one light emitting component. The light emitted from the light emitting component enters the light guide plate and exits from the surface of the light guide plate. The adhesive compound combines the light guide plates of the lighting panel modules. The adhesive compound can transmit the light within the light guide plates. | 05-28-2009 |
20100013054 | COMPOSITE MATERIAL SUBSTRATE - A composite material substrate having patterned structure includes a substrate, a first dielectric layer, a second dielectric layer, and a nitride semiconductor material. Herein, the first dielectric layer is stacked on the substrate, the second dielectric layer is stacked on the first dielectric layer, and the nitride semiconductor material is stacked on the second dielectric layer and is characterized by a plurality of patterns thereon. | 01-21-2010 |
20100041216 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures. | 02-18-2010 |
20100181577 | NITRIDE SEMICONDUCTOR SUBSTRATE - There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure. | 07-22-2010 |
Patent application number | Description | Published |
20090068773 | METHOD FOR FABRICATING PIXEL STRUCTURE OF ACTIVE MATRIX ORGANIC LIGHT-EMITTING DIODE - A method for fabricating an AMOLED pixel includes forming a transparent semiconductor layer on a substrate and forming a first channel layer of the switch TFT, a lower electrode of a storage capacitor and a second channel layer of a driving TFT. A first dielectric layer is formed over the substrate. A first opaque metal gate of the switch TFT, a second opaque metal gate of the driving TFT and a scan line are formed on the first dielectric layer. A first source and a first drain of the switch TFT are formed in the first channel layer and a second source and a second drain of the switch TFT are formed in the second channel layer. A patterned transparent metal layer is formed on the first dielectric layer. A data line is formed over the substrate. An OLED is formed over the substrate. | 03-12-2009 |
20100127254 | PHOTO SENSING ELEMENT ARRAY SUBSTRAT - A photo sensing element array substrate is provided. The photo sensing element array substrate includes a flexible substrate and a plurality of photo sensing elements. The photo sensing elements are disposed in array on the flexible substrate. Each of the photo sensing elements includes a photo sensing thin film transistor (TFT), an oxide semiconductor TFT and a capacitor. The photo sensing TFT is disposed on the flexible substrate. The oxide semiconductor TFT is disposed on the flexible substrate. The oxide semiconductor TFT is electrically connected to the photo sensing TFT. The capacitor is disposed on the flexible substrate and electrically connected between the photo sensing TFT and the oxide semiconductor TFT. When the photo sensing element array substrate is bent, it remains unaffected from normal operation. | 05-27-2010 |
20100148168 | INTEGRATED CIRCUIT STRUCTURE - An integrated circuit structure including a substrate, an insulating layer, a first transistor and a second transistor is provided. The insulating layer, the first transistor and the second transistor are disposed on the substrate. The first transistor includes a first gate, a first oxide semiconductor layer, a first source and a first drain. A portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal. The second transistor includes a second gate, a second oxide semiconductor layer, a second source and a second drain. A portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal. In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may have different thickness or different carrier concentrations. | 06-17-2010 |
20120164766 | METHOD OF FABRICATING AN ACTIVE DEVICE ARRAY AND FABRICATING AN ORGANIC LIGHT EMITTING DIODE ARRAY - Methods of fabricating active device array and organic light emitting diode array are provided. A first pattern metal layer is formed over a substrate. An oxide semiconductor layer is formed entirely over the substrate. A first insulation layer covering the first patterned metal layer and the oxide semiconductor layer is formed entirely on the substrate. A second patterned metal layer is formed on the first insulation layer. The oxide semiconductor layer and the first insulation layer is patterned by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer. A second insulation layer is entirely formed on the substrate. A second patterned oxide semiconductor layer is formed over the second insulation layer. A third patterned metal layer is formed over the second insulation layer. | 06-28-2012 |
20120171792 | METHOD OF FABRICATING A PIXEL ARRAY - A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern. | 07-05-2012 |
20130126859 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer. The first insulating layer is patterned by using the gate as an etching mask so as to expose the metal oxide semiconductor layer to serve as a source region and a drain region. A dielectric layer is formed on the substrate to cover the gate and the oxide semiconductor layer, where the dielectric layer has at least one of hydrogen group and hydroxyl group. A heating treatment is performed so that the at least one of hydrogen group and hydroxyl group reacts with the source region and the drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region respectively are formed on the dielectric layer. | 05-23-2013 |
20130161703 | SENSOR ELEMENT ARRAY AND METHOD OF FABRICATING THE SAME - A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern. | 06-27-2013 |
20140110715 | Thin Film Transistor Array Panel and Manufacturing Method Thereof - A thin film transistor (TFT) array display panel and a manufacturing method thereof are provided. The TFT array panel may comprise a substrate, a pixel array and an absorption layer. The substrate has an upper surface. The pixel array may be formed on the upper surface of the substrate and comprises several data lines, several scan lines and several active elements. The data lines and the scan lines define several pixel areas. Each active element is formed in the corresponding pixel area, and may comprise a channel layer. The absorption layer and the channel layer may be formed on the same layer structure. | 04-24-2014 |
20140312343 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer. The first insulating layer is patterned by using the gate as an etching mask so as to expose the metal oxide semiconductor layer to serve as a source region and a drain region. A dielectric layer is formed on the substrate to cover the gate and the oxide semiconductor layer, where the dielectric layer has at least one of hydrogen group and hydroxyl group. A heating treatment is performed so that the at least one of hydrogen group and hydroxyl group reacts with the source region and the drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region respectively are formed on the dielectric layer. | 10-23-2014 |
Patent application number | Description | Published |
20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
20110124193 | CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout. | 05-26-2011 |
20110230998 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
20110243424 | METHOD AND APPARATUS FOR MONITORING MASK PROCESS IMPACT ON LITHOGRAPHY PERFORMANCE - The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern. | 10-06-2011 |
20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
20130290912 | METHOD AND APPARATUS FOR MONITORING MASK PROCESS IMPACT ON LITHOGRAPHY PERFORMANCE - The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern. | 10-31-2013 |
20130292841 | SEMICONDUCTOR INTERCONNECT STRUCTURE - The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer. | 11-07-2013 |
20140189611 | Method Of Decomposable Checking Approach For Mask Alignment In Multiple Patterning - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count. | 07-03-2014 |
20140193981 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 07-10-2014 |
20140220493 | Self Aligned Patterning With Multiple Resist Layers - A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate. | 08-07-2014 |
20140248768 | Mask Assignment Optimization - A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines. | 09-04-2014 |
20140252433 | Multi-Layer Metal Contacts - A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact. | 09-11-2014 |
20140273363 | METHOD OF PATTERNING FEATURES OF A SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate. | 09-18-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20140273446 | Method of Patterning a Feature of a Semiconductor Device - A method including forming a first pattern having a first and second feature is described. A masking layer is formed over the first and second features. An opening is patterned in the masking layer. The opening can extend over at least one of the first and second features. The patterned opening is then used to form a third feature (filled trench) between the first and second features. A second pattern is then formed that includes a fourth feature and fifth feature each having an edge defined by the third feature. The first, second, fourth and fifth features may then be used to pattern an underlying layer over the semiconductor substrate. | 09-18-2014 |
20140273468 | PATTERNING METHOD FOR SEMICONDUCTOR DEVICE FABRICATION - A method includes forming a first pattern having a first opening on a semiconductor substrate. The first opening is then filled. A second pattern of a first and second feature, interposed by the filled opening, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the filled opening, the first feature and the second feature. After forming the spacer elements, the material comprising first and second features is removed to form a second opening and a third opening. The filled opening, the second opening and the third opening are used as a masking element to etch a target layer of the substrate. | 09-18-2014 |
20140377962 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 12-25-2014 |
Patent application number | Description | Published |
20120194900 | SECOND-HARMONIC GENERATION NONLINER FRENQUENCY CONVERTER - A second-harmonic generation nonlinear frequency converter includes a nonlinear optical crystal. The nonlinear optical crystal includes a plurality of sections. The sections connect to each other in sequence, and each section has a phase different from others. Each of the phases includes a positive domain and a negative domain. Each of the sections includes a plurality of quasi-phase-matching structures. The quasi-phase-matching structures connect to each other in sequence and have the same phase in one section. | 08-02-2012 |
20120228655 | LIGHT EMITTING DIODE WITH LARGE VIEWING ANGLE AND FABRICATING METHOD THEREOF - A light emitting diode includes a substrate, a plurality of pillar structures, a filler structure, a transparent conductive layer, a first electrode, and a second electrode. These pillar structures are formed on the substrate. Each of the pillar structures includes a first type semiconductor layer, an active layer, and a second type semiconductor layer. The first type semiconductor layers are formed on the substrate. The pillar structures are electrically connected with each other through the first type semiconductor layers. The filler structure is formed between the pillar structures. The filler structure and the second type semiconductor layers of the pillar structures are covered with the transparent conductive layer. The first electrode is in contact with the transparent conductive layer. The second electrode is in contact with the first type semiconductor layer. | 09-13-2012 |
20130178077 | CONNECTORS - An electrical connector, which is adapted to a printed circuit board (PCB) with a first connection port, comprises a bottom having a base and a conductive element mounted in an opening of the base, a second connection port disposing on the base, and a housing covering the bottom. When the bottom is disposed on the PCB, the first connection port is accommodated in the opening of the base, and an elastic strip of the conductive element presses on the first connection port toward a direction parallel to the PCB for combining the electrical connector and the first connection port on the PCB, and preventing the separation or loose connection of the electrical connector from the first connection port or the PCB. | 07-11-2013 |
20130260591 | CARD EDGE CONNECTOR - A card edge connector includes a body and two latches. The body includes a base and two columns. The base includes an insertion slot formed thereon, and the two columns are disposed on the base and located two opposite ends of the base. Each of the columns includes a trench connecting to the insertion slot. Two latches are respectively disposed to the two columns. Each of the fasten portions fixes one of the latches to the corresponding column, such that an elastic arm of the latch suspends in the trench of the corresponding column. The elastic arm includes an engaging portion for moving back and forth relative to the column in the trench. When a circuit board inserts into the insertion slot of the body, the engaging portions of the latches clamp the circuit board, so as to prevent the circuit board from escaping from the card edge connector. | 10-03-2013 |
20130288532 | EXPANSION MODULE AND A FRAME THEREOF - An expansion module, for electrically connecting an interface card to a circuit board, includes an electrical connector and a frame. One side surface of the electrical connector is disposed on the circuit board and an electrical slot is disposed on the other side surface of the electrical connector for one end of the interface card to be inserted therein. The frame includes a main body, a fixing portion, and a securing portion. The fixing portion and the securing portion are integrally extended from the main body. The fixing portion is detachably installed to the circuit board, and the securing portion is for the other end of the interface card to be detachably fixed thereon, so as to arrange the interface card upright on the circuit board and reduce area on the circuit board occupied by the interface card. | 10-31-2013 |
20140170883 | ELECTRICAL CONNECTOR - An electronic connector includes a body and a fixing member penetrating through the body. A fastening section of the fixing member is inserted in the body, and an extending section of the fixing member protrudes from the body. The fastening section withstands a block portion of the body toward the extending section inside the body. In this way, when the electronic connector is assembled with a circuit board, the body of the electronic connector is fixed to the circuit board by the fastening section of the fixing member, for avoiding the body separating from the fixing member. | 06-19-2014 |
20140187083 | CABLE MANAGEMENT APPARATUS - A cable management apparatus includes a housing and a plurality of partitions. The housing has a first side surface and a second side surface opposite to each other. The partitions are disposed in the housing to divide the interior of the housing into a plurality of compartments, and each compartment extends to the two faces of the housing. A plurality of signal cables are respectively disposed into the compartments, so that the signal cables are able to be disposed in the electronic slots through the housing and that the signal cables are electronically connected to the corresponding pins respectively. | 07-03-2014 |