Chih-Hao Chang
Chih-Hao Chang, Chiayi City TW
Patent application number | Description | Published |
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20110098164 | BALANCE TRAINING DEVICE - A balance training device includes at least one supporting base and at least one plank member. The supporting base includes a plank connecting portion formed with a plank coupling groove that opens upwardly. The plank coupling groove includes a first groove section and a second groove section that intersects the first groove section. The plank member includes a plate portion and a rib structure disposed on a bottom face of the plate portion. The rib structure removably engages the plank coupling groove of the supporting base. The rib structure includes a first rib part to engage the first groove section and a second rib part to engage the second groove section. | 04-28-2011 |
20110212425 | Modular Educational Device - A modular educational device includes primary and secondary modular boundary segments each having an outer shell extending to terminate at two socket ends, a plurality of modular plug-ended connectors each having two plug ends configured to mate with the corresponding ones of primary and secondary socket ends so as to enable the primary and secondary outer shell to form a loop-shaped structure that encircles an enclosed space of a certain geometric shape, and a modular support stand having a base and a pair of jaws which extend uprightly from the base and which are spaced apart from each other by a fitting space for accommodating a gripped region of the primary modular boundary segment so as to enable the loop-shaped structure to be stood on a surface. | 09-01-2011 |
Chih-Hao Chang, Chu-Bei City TW
Patent application number | Description | Published |
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20110024804 | METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SIGE STRESSOR - A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation. | 02-03-2011 |
20110068411 | Block Contact Plugs for MOS Devices - An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug. | 03-24-2011 |
20110193144 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack. | 08-11-2011 |
20110193178 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 08-11-2011 |
20110241084 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 10-06-2011 |
20120091528 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure. | 04-19-2012 |
20120104472 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material. | 05-03-2012 |
20130043507 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 02-21-2013 |
20130062669 | SILICIDE FORMATION AND ASSOCIATED DEVICES - Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers. | 03-14-2013 |
20130140637 | Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure. | 06-06-2013 |
20130175578 | IO ESD Device and Methods for Forming the Same - A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode. | 07-11-2013 |
20130187237 | STRUCTURE AND METHOD FOR TRANSISTOR WITH LINE END EXTENSION - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side. | 07-25-2013 |
20130196478 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 08-01-2013 |
20130224952 | Curved Wafer Processing on Method and Apparatus - An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like. | 08-29-2013 |
20130228866 | Semiconductor Devices and Manufacturing and Design Methods Thereof - Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin. | 09-05-2013 |
20130264643 | METHOD FOR FABRICATING A STRAINED STRUCTURE - A field effect transistor including a substrate which includes, a fin structure, the fin structure having a top surface. The field effect transistor further including an isolation in the substrate and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the fin structure and the isolation structure. The S/D recess cavity includes a lower portion, the lower portion further includes a first strained layer, a first dielectric film and a second dielectric film, wherein the first strained layer is disposed between the first dielectric film and the second dielectric film. The S/D recess cavity further includes an upper portion including a second strained layer overlying the first strained layer, wherein a ratio of a height of the upper portion to a height of the lower portion ranges from about 0.8 to about 1.2. | 10-10-2013 |
20130277744 | IO ESD Device and Methods for Forming the Same - A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode. | 10-24-2013 |
20130280899 | SILICIDE FORMATION AND ASSOCIATED DEVICES - Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers. | 10-24-2013 |
20130320452 | Semiconductor Device and Method of Forming the Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact. | 12-05-2013 |
20140001574 | IMPROVED SILICIDE FORMATION AND ASSOCIATED DEVICES | 01-02-2014 |
20140048888 | Strained Structure of a Semiconductor Device - A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region. | 02-20-2014 |
20140091362 | INTEGRATED CIRCUIT TRANSISTOR STRUCTURE WITH HIGH GERMANIUM CONCENTRATION SiGe STRESSOR - An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more. | 04-03-2014 |
20140147978 | Strained Structure of a Semiconductor Device - A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region. | 05-29-2014 |
20140175513 | Structure And Method For Integrated Devices On Different Substartes With Interfacial Engineering - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si | 06-26-2014 |
20140179077 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING SILICIDE LAYERS - A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess. A hard mask layer is formed over the gate electrode layer in the recess. Silicide layers are then formed on a source region and a drain region disposed in the semiconductor material region, while the hard mask is disposed over the gate electrode layer. A source contact and a drain contact is then provided, each source and drain contact being conductively coupled to a respective one of the silicide layers. | 06-26-2014 |
20150129990 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE - A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape. | 05-14-2015 |
20150270153 | Curved Wafer Processing Method and Apparatus - An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like. | 09-24-2015 |
20150348967 | Semiconductor Devices having Fin Field Effect Transistor (FinFET) Structures and Manufacturing and Design Methods Thereof - Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin. | 12-03-2015 |
20150380554 | METHOD FOR FABRICATING A STRAINED STRUCTURE AND STRUCTURE FORMED - A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer. | 12-31-2015 |
20160064381 | Fin-Like Field Effect Transistor (FinFET) Device And Method Of Manufacturing Same - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer. | 03-03-2016 |
20160104706 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material. | 04-14-2016 |
Chih-Hao Chang, Hsinchu TW
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20100034964 | Method of increasing beta-phase content in a conjugated polymer useful as a light emitting layer in a polymer light emitting diode - A simple and efficient method for transforming conformation of parts of chains in the amorphous phase in a conjugated polymer to extended conjugation length (termed as β phase) is disclosed. The β phase acts as a dopant and can be termed self-dopant. The generated self-dopant in the amorphous host allows an efficient energy transfer and charge trapping to occur and leads to more balanced charge fluxes and more efficient charge recombination. For example, a polyfluorene film was dipped into a mixed solvent/non-solvent, tetrahydrofuran/methanol in volume ratio of 1:1, to generate a β-phase content up to 1.32%. A polymer light emitting diode with the dipped polyfluorene film as a light emitting layer therein provides a more pure and stable blue-emission (solely from the self-dopant) with CIE color coordinates x+y<0.3 and a performance of 3.85 cd A | 02-11-2010 |
20150311818 | LOAD IMPEDANCE ESTIMATION AND REPETITIVE CONTROL METHOD CAPABLE OF ALLOWING INDUCTANCE VARIATION FOR INVERTER - The present invention provides a load impedance estimation and repetitive control method capable of allowing inductance variation for an inverter, wherein the method is applied for predicting corresponding next-period switching duty cycles for four switching member sets of the inverter by way of sampling three phase voltages and calculating next-period voltage compensations based on the previous line-period voltage compensations. Moreover, during the calculation and prediction, the method also involves the inductance variations of the output inductors of the inverter into the load impedance estimation matrix equation. Therefore, the three phases four wires inverter with the presented load impedance estimation and repetitive control method can provide a steady output voltage to the loads even if the originally-connected loads are replaced with other different loads. Thus, this load impedance estimation and repetitive control method can indeed improve the drawbacks of the inverter controller based on conventional DQ transformation method. | 10-29-2015 |
Chih-Hao Chang, Chung-Ho TW
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20090309979 | Image analysis using a hybrid connected component labeling process - A hybrid connected component labeling process for analyzing digitized or binary images includes the following steps. Firstly, a forward scan is executed to assign a forward label to each foreground pixel in the image. Then, a backward scan is executed to assign a backward label to each foreground. The backward labels are rearranged and label connection is recorded. A label allocation table including final labels and reference labels is provided for recording the use of the labels. When an object is considered as noise, the label corresponds to the pixels of the object is released by updating the label allocation table. | 12-17-2009 |
20090310822 | Feedback object detection method and system - A feedback object detection method and system. The system includes an object segmentation element, an object tracking element and an object prediction element. The object segmentation element extracts the object from an image according to prediction information of the object provided by the object prediction element. Then, the object tracking element tracks the extracted object to generate motion information of the object like moving speed and moving direction. The object prediction element generates the prediction information such as predicted position and predicted size of the object according to the motion information. The feedback of the prediction information to the object segmentation element facilitates accurately extracting foreground pixels from the image. | 12-17-2009 |
20090310823 | Object tracking method using spatial-color statistical model - An object tracking method utilizing spatial-color statistical models is used for tracking an object in different frames. A first object is extracted from a first frame and a second object is extracted from a second frame. The first object is divided into several first blocks and the second object is divided into several second blocks according to pixel parameters of each pixel within the first object and the second object. The comparison between the first blocks and the second blocks is made to find the corresponding relation therebetween. The second object is identified as the first object according to the corresponding relation. | 12-17-2009 |
Chih-Hao Chang, Taipei TW
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20080281243 | ADJUSTABLE JOINT SPLINT - An adjustable joint splint has a splint, two pads and an adjustable strap. The splint has two curved end segments and two connectors. The curved end segments are curved in the same direction and are parallel to each other, and each has an inner surface. The connectors connect the curved end segments. The pads are mounted respectively on the inner surfaces of the curved end segments. The adjustable strap is mounted between the connectors. Doctors can easily adjust the adjustable strap and the splint to conform to joints of different patients, patients can also tighten or loosen the strap around their joints themselves, and the splint has an opening that provides good ventilation. Therefore joints are held securely and comfortably by the splint, and skin in the area of the immobilized joint does not become irritated. | 11-13-2008 |
20090001875 | ORGANIC LIGHT-EMITTING DEVICE INCORPORATING MULTIFUNCTIONAL OSMIUM COMPLEXES - Fabrication of organic light-emitting devices is disclosed by employing the efficient, multifunctional orange-red emitting osmium complex in combination with a second phosphorescent complex showing strong emission at the shorter wavelength region such as blue or blue-green emitting iridium (Ir) complex. The present invention provides WOLEDs with forward viewing efficiencies up to (17% photon/electron, 35.6 cd/A, 28 lm/W) and total peak external efficiencies up to (28.8%, 47.5 lm/W), giving the conceptual design for the highly efficient and color-stable phosphorescent WOLEDs. | 01-01-2009 |
Chih-Hao Chang, Taichung TW
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20080277144 | METHOD FOR INDICATING QUALITY OF A CIRCUIT BOARD - A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good. | 11-13-2008 |
Chih-Hao Chang, Chu-Bei TW
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20110272739 | METHOD FOR FABRICATING A STRAINED STRUCTURE - A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film. | 11-10-2011 |
Chih-Hao Chang, Tu-Cheng TW
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20120047303 | DOCKING STATION - A docking station includes a multiplexer. The multiplexer includes a first input end, a second input end, and an encode system. The encode system is connected to the second input end, and configured to generate an encoding according to a connection status of the second input end. The encode system is configured to generate a first encoding, when a first peripheral device is connected to the second input end, to switch the multiplexer to a first state, in which the second input end is on and the first input end is off. The encode system is further configured to generate a second encoding, when the first peripheral device is not connected to the second input end, to switch the multiplexer to a second state, in which the second input end is off and the first input end is on. | 02-23-2012 |
20120058654 | CONNECTOR ASSEMBLY - A connector assembly for connecting a peripheral device to a computer includes a male connector having a plurality of first connecting pins and a female connector having a plurality of second connecting pins. The plurality of first connecting pins is configured to connect to the peripheral device. The plurality of second connecting pins is configured to connect to the computer. The plurality of second connecting pins is defined on the first circuit board in a second row and a third row. The plurality of second connecting pins comprises a plurality of differential pairs, and each differential pair comprises two differential transmission lines. The two differential transmission lines of each of the plurality of differential pairs are defined on a single row of the second and third rows. | 03-08-2012 |
20120062309 | POWER SUPPLY CIRCUIT - A power supply circuit for protecting a battery from current leakage when the battery is not in use includes a control signal input circuit and a switch circuit. The control signal input circuit receives a first control signal from a chip and output a second control signal. The switch circuit receives the second control signal and turns on or off an electronic connection between the battery and the chip. Wherein when the battery is not in use and not being charged by the adaptor, there is a possibility of current leakage from the battery. In such case, the switch circuit turns off the electronic connection between the battery and the chip, and the battery does not provide power to the chip. | 03-15-2012 |
20120162531 | HDMI AND VGA COMPATIBLE INTERFACE CIRCUIT - A signal transmitting circuit includes a HDMI signal transmitting unit adapted to output a HDMI signal, a VGA signal transmitting unit adapted to output a VGA signal, a VGA signal processing unit, and a transmitting control unit. The VGA signal processing unit is connected to the VGA signal transmitting unit. The VGA signal processing unit is adapted to receive the VGA signal from the VGA signal transmitting unit, and include a detection signal into the VGA signal to form a combination signal. A transmitting control unit is connected to the VGA signal processing unit and the HDMI signal transmitting unit. The transmitting control unit is adapted to receive the combination signal and the VGA signal, to distinguish the combination signal and the VGA signal, and to output the combination signal and the VGA signal to the appropriate receivers. | 06-28-2012 |
Chih-Hao Chang, Raleigh, NC US
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20120057235 | Method for Antireflection in Binary and Multi-Level Diffractive Elements - Methods and apparatus for reducing or eliminating reflection at the interface between a binary or multi-level diffractive element and a surrounding medium. A non-planar diffractive surface of a diffractive optical element is coated forming a plurality of nanostructures on the non-planar diffractive surface and, in certain embodiments, on a planar surface as well. The nanostructures are chosen for providing adiabatic refractive index matching at the optical interface between the non-planar diffractive surface and a surrounding medium subject to matching tangential fields at surface discontinuities. | 03-08-2012 |
Chih-Hao Chang, Chu-Nan TW
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20120092873 | LED LAMP HAVING WATERPROOF STRUCTURES - An exemplary LED lamp includes a heat sink, an LED module mounted on the heat sink and a lens covering the LED module. The heat sink has a top surface and a bottom surface opposite to the top surface. The LED module is mounted on the top surface of the heat sink. A waterproof groove is defined in the top surface of the heat sink. The groove has an inner wall adjacent to the LED module and an outer wall far away from the LED module. The inner wall is higher than the outer wall. The lens has a downwardly extending flange inserted into the groove. A waterproof ring is received in the groove and pressed by the flange. | 04-19-2012 |
20120092879 | LAMP INCORPORATING CLIPS - A lamp includes a housing, a cover mounted on the housing, a light source received between the housing and the cover and a plurality of clips fixing the housing to the cover. Each clip has two opposite ends pressing against a top face of the housing and a bottom face of the cover, respectively, and a middle bent inwardly towards the housing. The housing includes a top wall having a plurality of slots to receive corresponding ends of the clips and a sidewall extending downwardly from the top wall to be pressed by the middles of the clips. The cover includes a bottom plate and a flange extending upwardly from the bottom plate. The flange defines a plurality of depressions adjacent to the bottom plate to receive the other ends of the clips. | 04-19-2012 |
20130128579 | ILLUMINATING DEVICE - An illuminating device comprises a heat dissipating module, a light emitting module arranged on the heat dissipating module, and a holder connected to the heat dissipating module. The heat dissipating module comprises a heat conductive plate and a plurality of fins; the heat conductive plate has a first surface and a second surface opposite to the first surface; the plurality of fins are configured on the first surface and extends along a direction away from the second surface. The light emitting module comprises a base attached to the second surface of the heat dissipating module and a light source; the base has a supporting surface and the light source is arranged on the supporting surface. A distance between the supporting surface and the second surface gradually increases along a direction from one side of the heat conductive plate to the other. | 05-23-2013 |
Chih-Hao Chang, Tainan City TW
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20120224403 | METHOD FOR CONTROLLING THREE-PHASE CURRENT CONVERTER - A method is for controlling a three-phase current converter. First, subtract a second reference current signal representing the predicted current of the three-phase terminals in the present switching cycle from a first reference current signal representing the predicted current of the three-phase terminals in the next switching cycle to obtain a predicted variation. Then, subtract a feedback current signal representing the feedback current of the three-phase terminals in the previous switching cycle from the second reference current signal delayed by one switching cycle to obtain a current error. Multiply the current error by an error coefficient then add the predicted variation to obtain a current variation. Finally, obtain duty ratios of a plurality of switches, according to the current variation and inductance of the first to the third inductor. The three-phase current converter converts electric power between a DC terminal and the three-phase terminals, according to the duty ratio. | 09-06-2012 |
20150207433 | SINGLE-PHASE THREE-WIRE POWER CONTROL SYSTEM AND POWER CONTROL METHOD THEREFOR - The present disclosure provides a single-phase three-wire power control system integrating the electricity of a DC power supply device to an AC power source. The single-phase three-wire power control system comprises a single-phase three-wire inverter, a driving unit, a sampling unit and a processing unit. The single-phase three-wire inverter coupled between the DC power supply device and the AC power source converts a DC voltage of the DC power supply device to an output voltage. The driving unit is coupled to the single-phase three-wire inverter. The sampling unit samples the inductor current of an inductor of the single-phase three-wire inverter. The processing unit which is coupled to the driving unit and the sampling unit controls the single-phase three-wire inverter through the driving unit. The processing unit obtains the duty ratio according to the inductance of the inductor, the total variation of the inductor current, the DC voltage and the output voltage. | 07-23-2015 |
Chih-Hao Chang, New Taipei City TW
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20120243206 | Display and electronic device having the same - A display includes an outer casing, two backlight modules, and a flexible display panel. The outer casing includes at least one connecting member having two connecting ends respectively disposed at left and right sides thereof, and two casing panels connected respectively to the connecting ends and respectively having bonding faces. The two backlight modules are disposed respectively on the bonding faces of the casing panels. The flexible display panel includes two side panel sections disposed respectively on the backlight modules, and a foldable intermediate section connected between the side panel sections. The casing panels are pivotal relative to each other to move the backlight modules and the flexible display panel to an unfolded position. The backlight modules coplanarly cover a backside of the flexible display panel in the unfolded position. | 09-27-2012 |
20120243207 | Display for electronic device - A display includes a flexible display panel having a back face, two backlight modules disposed on the back face of the display panel and each including a contact end, and an outer casing having two casing panels respectively connected to and supporting the backlight modules oppositely of the display panel. The casing panels are pivotal relative to each other to move the backlight modules and the display panel between collapsed and non-collapsed positions. In the collapsed position, the display panel is folded, and the backlight modules are parallelly spaced apart. In the non-collapsed position, the display panel is laid flat, the backlight modules coplanarly cover the back face of the display panel, and the contact ends of the backlight modules abut against each other. | 09-27-2012 |
20130084663 | METHOD FOR FABRICATING PHOTO SPACER AND LIQUID CRYSTAL DISPLAY AND ARRAY SUBSTRATE - A method for fabricating a photo spacer and an array substrate having the photo spacer are provided. At least one exposure process, a developing process, and a baking process are performed to a photo-sensitive material layer formed a substrate to fabricate a photo spacer, wherein the at least one exposure process includes a back side exposure process. The substrate has a light transmitting region and a light shielding region so that the photo-sensitive material layer is defined into a first block and a second block after the back side exposure process. The developing process is performed to at least remove the second block. A front side exposure process is performed to the first block. The baking process is performed to cure the first block of the photo-sensitive material layer to form a photo spacer. | 04-04-2013 |
20130163278 | ELECTRONIC DEVICE HAVING A FLEXIBLE SCREEN, A BACKLIGHT MODULE AND A LIGHT GUIDE PLATE - An electronic device includes a base having two opposite sidewalls, two carriers connected pivotally and respectively to the sidewalls, and two light guide plates respectively disposed on the carriers. The carriers are rotatable relative to the base between a first position, where the carriers cooperatively define a carrier surface, and a second position, where the carriers are parallel to each other. A flexible screen is superposed on the light guide plates, is expanded to a planar state when move along with the carriers to the first position, and is folded when move along with the carriers to the second position. | 06-27-2013 |
20140268297 | FLEXIBLE LIQUID CRYSTAL DISPLAY AND FLEXIBLE FLUID DISPLAY - A flexible liquid crystal display and a flexible fluid display are provided. The flexible liquid crystal display includes a first module, a second module, at least two supporting structures and a liquid crystal layer. The second module is disposed correspondingly to the first module. The supporting structures are separately disposed between the first module and the second module and used for abutting the first module and the second module, so that a space between the first module and the second module is divided into a flexible area and two non-flexible areas. The flexible area is located between the two non-flexible areas. The liquid crystal layer is disposed in the flexible area and the two non-flexible areas. | 09-18-2014 |
20150097573 | LOAD APPARATUS FOR TESTING - A load apparatus for testing is provided. The load apparatus for testing includes a first comparison circuit, a switch circuit, a voltage-dividing load circuit and a second comparison circuit. The first comparison circuit receives an input voltage from an input terminal and obtains a first sensing voltage according to the input voltage, and compares whether the first sensing voltage is greater than a first reference voltage for providing a first sensing signal. The switch circuit receives the first sensing signal and the input voltage. The switch circuit guides the input voltage to the voltage-dividing load circuit according to the first sensing signal. The voltage-dividing load circuit generates a second sensing voltage according to an input current generated at the input terminal. The second circuit is coupled to the voltage-dividing load circuit and compares whether the input current is greater than a reference current for providing a testing signal. | 04-09-2015 |
Chih-Hao Chang, Hsinchu City TW
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20120293759 | SWITCHABLE THREE-DIMENSIONAL DISPLAY - A switchable three-dimensional (3D) display includes a display device and a switchable parallax barrier that is disposed on the display device. The switchable parallax barrier includes a first electrode structure, a second electrode structure, and a liquid crystal layer. The liquid crystal layer is located between the first electrode structure and the second electrode structure. The first electrode structure includes a planar electrode, a plurality of first bar electrodes electrically connected to one another, and an insulating layer. A partial region of the planar electrode is not covered by the first bar electrodes. The insulating layer is disposed between the planar electrode and the first bar electrodes, so that the planar electrode is electrically insulated from the first bar electrodes. | 11-22-2012 |
20160065089 | THREE-PHASE CURRENT CONVERTER WITH VARIED INDUCTANCES AND THREE-PHASE D-SIGMA CONTROL METHOD THEREOF - A three-phase current converter and a three-phase D-Σ control method with varied inductances are provided. In this method, two current variations of a first phase current, a second phase current and a third phase current flowing through a first inductor, a second inductor and a third inductor of the three-phase current converter respectively and two phase voltages of a first phase voltage, a second phase voltage and a third phase voltage are obtained. A first calculation is executed according to inductances of the inductors, the current variations and a switching period of a vector space modulation to obtain a calculation result. A second calculation is executed according to the phase voltages and the calculation result to obtain a duty ratio of the switching period of switch sets of the three-phase current converter. The inductances vary with the phase currents respectively. | 03-03-2016 |
Chih-Hao Chang, Hsinchu County TW
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20120320072 | Data Access Method and Electronic Apparatus for Accessing Data - A data access method applicable to a storage apparatus for reducing or eliminating an image tearing effect includes defining at least one write check point; comparing an actual write speed for writing data into the storage apparatus with a predetermined write speed at the write check point; and adjusting the actual write speed when a difference between the actual write speed and the predetermined write speed is larger than a predetermined value, for adaptively reducing the difference to be smaller than or equal to the predetermined value. | 12-20-2012 |
Chih-Hao Chang, Cambridge, MA US
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20130025322 | PROCESS FOR MAKING NANOCONE STRUCTURES AND USING THE STRUCTURES TO MANUFACTURE NANOSTRUCTURED GLASS - Fabrication method. At least first and second hardmasks are deposited on a substrate, the thickness and materials of the first and second hardmask selected to provided etch selectivity with respect to the substrate. A nanoscale pattern of photoresist is created on the first hardmask and the hardmask is etched through to create the nanoscale pattern on a second hardmask. The second hardmask is etched through to create the desired taper nanocone structures in the substrate. Reactive ion etching is preferred. A glass manufacturing process using a roller imprint module is also disclosed. | 01-31-2013 |
Chih-Hao Chang, Shenzhen CN
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20130092083 | PHOTORESIST COATER CARRYING SYSTEM AND PHOTORESIST COATER HAVING THE SAME - The present invention relates to a photoresist coater, which includes a receiving space consisting a top slab and a bottom slab, supporting pins and a carrying tray disposed in the receiving space. The supporting pins are coupled to the carrying tray. The photoresist coater further includes an adjustment mechanism disposed in the receiving space for automatically adjusting a height of the carrying tray. The adjustment mechanism is coupled to the carrying tray. The present invention further relates to a photoresist coater carrying system. The carrying system and the corresponding photoresist coater have a simpler way of operation and higher adjustment accuracy. | 04-18-2013 |
Chih-Hao Chang, New Taipei TW
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20130335296 | PANEL ANTENNA - A panel antenna includes a panel portion and a feeder cable. The panel portion includes a first portion and a second portion connected with the first portion to form a L-shape. A first metal sheet is disposed on the first portion. A second metal sheet is disposed on the second portion. The first and second metal sheets connect with each other. The first metal sheet has a feeding point and the second metal sheet has an elongate connecting arm. The overall structure of the first and second metal sheets forms a L-shape The feeder cable includes an inner conductor electrically connecting with the feeding point and an outer conductor extending along the connecting arm. The outer conductor has an exposed part contacted with the connecting arm. | 12-19-2013 |
Chih-Hao Chang, Douliu City TW
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20130201184 | VIEW SYNTHESIS METHOD CAPABLE OF DEPTH MISMATCHING CHECKING AND DEPTH ERROR COMPENSATION - A view synthesis method of depth mismatching checking and depth error compensation, wherein, input left and right maps are warped in a processor to perform view synthesis, comprising following steps: when a present pixel moves to a position of a target pixel after warping, compute respectively pixel displacement amounts for said present pixel to move to said target pixel in said left and said right maps, to figure out coordinate of said target pixel; determine if depth value of the present pixel is greater than that of said target pixel, if an answer is positive, determine if depth value of said present pixel matches that of coordinate adjacent to said target pixel; and if answer is negative, set depth value of said target pixel to a hole; otherwise, cover said target pixel with pixel value of said present pixel, hereby completing refining even minute errors. | 08-08-2013 |
Chih-Hao Chang, Longtan Township TW
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20130167896 | THERMOELECTRIC MODULE AND METHOD OF FABRICATING THE SAME - The disclosure provides a thermoelectric module and a method for fabricating the same. The thermoelectric module includes a plurality of p-type and n-type segmented thermoelectric elements disposed in a planar array, wherein the p-type and n-type segmented thermoelectric elements are coupled in series via a plurality of first electrodes and second electrodes. Each segmented thermoelectric element includes at least two vertically homogeneous thermoelectric segments, and at least two adjacent thermoelectric segments have a fusion-bonding layer therebetween. The fusion-bonding layer includes a tin-containing material and a plurality of spacers disposed among the tin-containing material, wherein the melting point of the spacers is higher than the liquidus temperature of the tin-containing material. | 07-04-2013 |
Chih-Hao Chang, Hsinchu Hsien TW
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20140218381 | IMAGE ACCESS METHOD AND IMAGE ACCESS APPARATUS - An image access method applicable to an image access device is provided. The method includes: providing a plurality of codes that respectively represent a plurality of image sources; determining a plurality of sets of access settings according to a pixel format arrangement, each set of access setting corresponding to a code arrangement combination composed of the codes; and sequentially accessing data of the image sources by the image access apparatus according to the code arrangement combinations corresponding to the access settings. | 08-07-2014 |
20140292546 | DECOMPRESSION CIRCUIT AND ASSOCIATED DECOMPRESSION METHOD - A decompression circuit includes a first decompression unit and a second decompression unit. The first decompression unit performs a first decompression operation on data to generate first decompressed data. The first decompressed data includes a plurality of literals and a distance-length pair. The second decompression unit receives the first decompressed data, and sequentially performs a second decompression operation on the literals and the distance-length pair to generate second decompressed data. After the second decompression unit receives the distance-length pair from the first decompression unit and before the second decompression unit completes decompressing the distance-length pair, the second decompression unit transmits data required for the subsequent first decompression operation performed by the first decompression unit to the first decompression unit according to the distance-length pair. | 10-02-2014 |
20140292547 | DECOMPRESSION CIRCUIT AND ASSOCIATED COMPRESSION METHOD AND DECOMPRESSION METHOD - A decompression circuit for decompressing data includes a first decompression unit and a second decompression unit. The data sequentially includes a compressed first string, a compressed distance-length pair and a compressed second string. The first decompression unit performs a first decompression on the data to obtain a first string, a distance-length pair and a second string. The second decompression unit receives and decompresses the first string, the distance-length pair and the second string. The first decompression unit does not involve data associated with the distance-length pair when decompression the second string. | 10-02-2014 |
Chih-Hao Chang, Yuanlin Township TW
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20140295354 | MANUFACTURING METHOD OF MICROSTRUCTURE - A manufacturing method of microstructure comprises steps of: a motion determination step which determines the motion of a substrate relative to at least a photomask; a microlens determination step which determines the profile of a microlens unit on the substrate; an analysis step which calculates the feature of the photomask according to the motion of the substrate and the profile of the microlens unit by using a numerical analysis method; a production step which produces the photomask according to the feature of the photomask; driving the substrate to do the motion determined in the motion determination step, and meanwhile making a laser light illuminate the substrate through the photomask to manufacture the microlens unit on the substrate by the superposition effect of the laser light; and performing a photolithography process by using the microlens unit to produce a microstructure on a photoresist substrate. | 10-02-2014 |
Chih-Hao Chang, Zhubei City TW
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20140340413 | LAYER ACCESS METHOD, DATA ACCESS DEVICE AND LAYER ACCESS ARRANGEMENT METHOD - A data access method is provided. The data access method is applied for a data device access device to access data from N layers to display an image, where N is a positive integer. Each of the N layers includes a horizontal start point, a horizontal end point, a vertical start point and a vertical end point. The data access method includes: dividing the image into a plurality of regions according to the horizontal start points, the horizontal end points, the vertical start points and the vertical end points, wherein the regions respectively correspond to the N layers; and accessing data from the respective layers corresponding to the regions when displaying the image. | 11-20-2014 |
Chih-Hao Chang, Shenzhen City CN
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20140356543 | Spray Nozzle, Spraying Device Having the Spray Nozzle and Method for Spraying - The present invention provides a spray nozzle, configured with left and right halves, at least one of the left and right halves being defined with a mating surface in which a recess defining width of a linear opening of the nozzle is defined, each end of the nozzle being mounted with fenders jointly define the linear opening of the nozzle along with the recess, wherein the mating surface in which the recess is defined further includes with a N number of partitions dividing the recess into a N+1 number of individual ejectors, wherein N is a positive integer. The present invention is to divide a single mouth of a spray nozzle of larger dimension into a plurality of individual ejectors with smaller dimension. During the acceleration or reduction of the spray nozzle, each individual ejector will deliver a homogeneous and even quantity of working liquid at central and end portions. The present invention further provides a spraying apparatus incorporated with such spray nozzle and a method for operating the spray nozzle. | 12-04-2014 |
Chih-Hao Chang, Chu-Beui City TW
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20150017768 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact. | 01-15-2015 |
Chih-Hao Chang, Cary, NC US
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20150098984 | NANOLITHOGRAPHY USING LIGHT SCATTERING FROM PARTICLES AND ITS APPLICATIONS IN CONTROLLED MATERIAL RELEASE - The present disclosure provides hollow nanostructures, methods of forming thereof, and methods of delivery of further nanomaterials utilizing the hollow nanostructures. The hollow nanostructures can be formed by illuminating particles, such as spherical particles, to create a scattering pattern that can be captured on, for example, a photoresist. Thus formed nanoparticles can have a substantially frusto-conical shape that can be tailored based on a variety of factors, including, for example, particle size, particle shape, light exposure characteristics, and light polarization. | 04-09-2015 |
Chih-Hao Chang, Hsin-Chu TW
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20150115373 | STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE ACTIVE REGIONS - A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region. | 04-30-2015 |
Chih-Hao Chang, Yunlin County TW
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20150162077 | STATIC MEMORY CELL - A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data. | 06-11-2015 |
Chih-Hao Chang, Taipei City TW
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20150191628 | CHEMICAL FILM ON SUBSTRATE, METHOD OF FORMING THE SAME, AND METHOD OF FORMING N-HYDROXYSUCCINIMIDE ESTER-FUNCTIONALIZED PARACYCLOPHANE - The present invention provides a method of forming N-hydroxysuccinimide ester-functionalized paracyclophane. The present method is carried out by adding 4-carboxyl-paracyclophane into N,N′-Dicyclohexylcarbodiimide (DCC) and N-Hydroxysuccinimide (NHS) to form N-hydroxysuccinimide ester-functionalized paracyclophane. The present invention further provides a chemical film on a substrate and a method of forming the same, wherein the chemical film includes N-hydroxysuccinimide ester-functionalized poly-para-xylylene. | 07-09-2015 |
20150252162 | ANTI-MICROBIAL MODIFIED MATERIAL AND ANTI-MICROBIAL MODIFICATION METHOD - The present invention concerns an anti-microbial modified material and an anti-microbial modification method, obtained by a bonding of a compound represented by formula (I) with a benzoyl-containing photoinitiator via a photoreaction. For the substrate surface modified by the anti-microbial modification method of the invention, the formation of the biofilm can be drastically diminished and a strong bactericidal capability may be afforded. | 09-10-2015 |
20150261268 | HEAT DISSIPATING SYSTEM USING FANS - This disclosure discloses a heat dissipating system using fans for an electronic device. The electronic device includes a first air outlet and a second air outlet. The heat dissipating system using fans includes a processor, a first fan, a second fan, an orientation sensor, and a temperature sensor. The orientation sensor is for sensing whether the electronic device is under a horizontal state or a vertical state and generating a corresponding orientation signal. The temperature sensor is for sensing the temperature of the electronic device and generating a temperature signal. When the temperature signal is greater than or equal to a predetermined value, the processor activates the first fan and the second fan. When the temperature signal is less than the predetermined value, the processor selectively activates one of the first fan and the second fan according to handedness information and the orientation signal. | 09-17-2015 |
Chih-Hao Chang, Shenzhen, Guangdong CN
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20160107184 | SLIT NOZZLE CLEANING DEVICE - The present invention discloses a slit nozzle cleaning device, the slit nozzle cleaning device comprises a scraper for cleaning the slit nozzle and an auxiliary inserting means, wherein the auxiliary inserting means is configured to guide the scraper into the slit nozzle. With the aid of the auxiliary inserting means, the scraper can enter the slit nozzle smoothly and precisely without the risk of breaking. | 04-21-2016 |