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| 20150138474 | LIQUID CRYSTAL DISPLAY WITH ULTRA-NARROW FRAME AND COF PACKAGING STRUCTURE OF DRIVING CIRCUIT THEREOF - The present invention provides an ultra-narrow frame liquid crystal display and a COF packaging structure for driving circuits in the ultra-narrow frame liquid crystal display. The COF packaging structure comprises: a sheet of flexible circuit board, with one side thereof bonded with a frame area of a glass substrate of the liquid crystal display, serving as a carrier sheet for chip-on-film flexible packaging; and a plurality of driving chips, bonded with the sheet of flexible circuit board sequentially along a scan direction, wherein a signal circuit between adjacent driving chips is arranged on the sheet of flexible circuit board. The present invention proposes a novel COF packaging structure, wherein the signal circuits required between the driving ICs are relocated to the COF flexible circuit board from the glass substrate by using the sheet of flexible circuit board. By mean of this, a voltage drop caused by increase of the resistance of wires between the driving ICs in the case of the large-sized narrow frame design may be avoided, thereby the mura of the panel due to a drop of input voltage to the driving ICs caused by the narrow frame large-sized panel can be avoided, and the quality of the product is improved. | 05-21-2015 |
| 20150162946 | GLASS SUBSTRATE FOR DISPLAY AND MANUFACTURING METHOD THEREOF - The present disclosure relates to the field of liquid crystal display, and particularly to a glass substrate for a display. The glass substrate is treated through a vapor deposition apparatus, and includes an optical compensation film. The optical compensation film has a relatively higher transmittance in a compensation area than in other areas, and the shape and position of the compensation area are configured to be consistent with a non-uniform heated area caused by the vapor deposition apparatus on the glass substrate. The present disclosure further relates to a corresponding method for manufacturing the glass substrate. According to the present disclosure, the defects of the glass substrate can be accurately overcome and the mura phenomenon of the display panel can be reduced. | 06-11-2015 |
| 20150206494 | SELF-ADAPTIVE MULTI-REGION COMMON VOLTAGE REGULATION SYSTEM AND METHOD - The present disclosure discloses a system of self-adaptively adjusting Multi-area common voltage, comprising a plurality of photosensitive devices, for sensing luminous quantity from the different areas so as to obtain and transmit flicker values corresponding to the different areas; a multiplexing element, connected with the plurality of photosensitive devices; a calculation and comparison unit, for continuously receiving the flicker values which are sensed by the plurality of photosensitive devices in a time sequence, calculating actual display condition, and comparing the actual display condition with an optimal display condition; and an common voltage adjusting and outputting unit, connected with the calculation and comparison unit, for adjusting the value of the current output common voltage if the optimal display condition is not met and remaining the value of the current output common voltage unchanged if the optimal display condition is met. The present disclosure can achieve automatically adjustment of the common voltage and thus increase the productivity. | 07-23-2015 |
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| 20100259932 | LIGHT EMITTER WITH HEAT-DISSIPATING MODULE - A light emitter with heat-dissipating module includes a light unit, a first heat-dissipating member, a second heat-dissipating member and a fastening member. The light unit includes a light-emitting element and a supporting plate having a pair of opposite surfaces. The first heat-dissipating member includes a first combining surface and a heat-dissipating portion. The first combining surface contacts with one of said two opposite surfaces of the supporting plate. The second heat-dissipating member includes a second combining surface and a heat-dissipating portion. The second combining surface contacts with the other of said two opposite surfaces of the supporting plate. The fastening member couples to the supporting plate, the first heat-dissipating member and the second heat-dissipating member to fix the combination of the supporting plate and the first and second heat-dissipating members. | 10-14-2010 |
| 20100295436 | LAMP - A lamp includes a housing, a heat sink, a light emitter, a fan and a blocking ring. The housing has an air inlet portion and an air outlet portion formed in a wall of the housing. The heat sink includes a base plate and a plurality of fins surrounding the base plate to define a compartment. Each of the fins have a first end facing the air inlet portion of the housing and a second end connecting with the base plate. The light emitter is fixed to the base plate of the heat sink. The fan is fixed inside the compartment of the heat sink. The blocking ring is mounted between the air inlet portion and the heat sink. Accordingly, the blocking ring blocks part of the heated airflow from flowing back to the air inlet portion and turbulence is avoided effectively. Therefore, the airflow inside the housing can flow smoothly through the air outlet to transfer heat to the environment and heat dissipating efficiency is enhanced. | 11-25-2010 |
| 20110279981 | Heat Dissipating Assembly - A heat dissipating assembly includes a circuit board having opposite first and second faces. The circuit board further includes a through-hole extending from the first face through the second face. A heat generating element is mounted on the first face of the circuit board and electrically coupled to the circuit board. The heat generating element includes a heat conducting portion aligned with the through-hole. A heat dissipating unit includes a base having an engaging face in contact with the second face of the circuit board. A metal solder is filled in the through-hole. The metal solder is engaged with the engaging face of the base and the heat conducting portion of the heat generating element. The heat generating element is directly engaged with the heat dissipating unit by the metal solder to effectively enhance the overall heat dissipating efficiency while reducing the number of members to lower the manufacturing costs. | 11-17-2011 |
| 20110284199 | Cooling Module - A cooling module comprises a heat sink, a cooling fan, a control assembly, a temperature sensor and a resilient heat conductor. The cooling fan facilitates cooling efficiency of the heat sink. The control assembly has a circuit board controlling rotation of the cooling fan. The temperature sensor is coupled to the circuit board of the control assembly and has a sensing face. The resilient heat conductor is disposed between the heat sink and the temperature sensor and has a first contact face and a second contact face, wherein the first contact face contacts the sensing face of the temperature sensor and the second contact face contacts a face of the heat sink. | 11-24-2011 |
| 20110292614 | Cooling Module Assembly Method - A cooling module assembly method comprises forming at least one through-hole on a circuit board; coupling the circuit board to a heat dissipating unit so that a face of the circuit board is coupled to a coupling face of the heat dissipating unit; filling the at least one through-hole with metal solders; fixing at least one heat-generating element to another face of the circuit board, wherein the at least one heat-generating element aligns with and covers the at least one through-hole; and soldering the at least one heat-generating element and the heat dissipating unit together by melting the metal solders in the at least one through-hole. | 12-01-2011 |
| 20110310559 | Heat Dissipating Assembly - A heat dissipating assembly includes a circuit board having opposite first and second faces. The circuit board further includes a through-hole extending from the first face through the second face. A heat generating element is mounted on the first face of the circuit board and electrically coupled to the circuit board. The heat generating element includes a heat conducting portion aligned with the through-hole. A heat dissipating unit includes a base having an engaging face in contact with the second face of the circuit board. A heat conducting adhesive is filled in the through-hole. The heat conducting adhesive is engaged with the engaging face of the base and the heat conducting portion of the heat generating element. The heat generating element is directly engaged with the heat dissipating unit by the heat conducting adhesive to effectively enhance the overall heat dissipating efficiency while reducing the number of members to lower the manufacturing costs. | 12-22-2011 |
| 20120081911 | LAMP - A lamp includes a housing, a heat sink, a light emitter, a fan and a blocking ring. The housing includes first and second shells, with the first shell forming a light-transparent portion and a first engaging portion. An air outlet portion is formed in a wall of the first shell, with the second shell forming a second engaging portion and a base. An air inlet portion is formed in a wall of the second shell. The heat sink includes a base plate and a plurality of fins defining a compartment. Each of the fins has first and second ends. The light emitter is electrically connected to the base. The blocking ring is mounted inside the housing. The blocking ring has two sides forming first and second flanges. The blocking ring further includes a side forming a protrusion ring and partially covering an outer periphery of the heat sink. | 04-05-2012 |
| 20130149128 | Advection-type Fan And An Impeller Thereof - An impeller of an advection-type fan includes a metal base plate, a shaft and a plurality of plastic blades. The metal base plate includes a shaft-coupling portion and a peripheral portion, with a first plane facing in a first direction and a second plane facing in a second direction opposite to the first direction arranged between the shaft-coupling portion and the peripheral portion. The metal base plate is in a plane form between the shaft-coupling portion and the peripheral portion. The shaft has a fixing end and a free end. The fixing end is coupled with the shaft-coupling portion and the free end extends in the first direction. Each plastic blade has a coupling portion and an air-driving portion. The coupling portion is coupled with the peripheral portion and the air-driving portion extends in the second direction. | 06-13-2013 |
| 20130243628 | Advection Fan and An Impeller Thereof - An impeller includes a metal base plate, a shaft and a plurality of plastic blades. The metal base plate includes a shaft-coupling portion, a peripheral portion, and first and second surfaces. The first surface faces away from the second surface in a first direction, the second surface faces away from the first surface in a second direction. The metal base plate is flat between the shaft-coupling portion and the peripheral portion. The first surface has a permanent magnet. The shaft has a fixing end coupled with the shaft-coupling portion, as well as a free end extending axially in the first direction. Each plastic blade has a coupling portion coupled with the peripheral portion, as well as an air-driving portion axially extending in the second direction. The impeller may be rotatably coupled with a driving module. The driving module is installed in a fan frame to form an advection fan. | 09-19-2013 |
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| 20090009198 | PROBING DEVICE - A probing device includes a rack that has an outer support member supporting a circuit layer and a center support member supporting a probe assembly. When the tester touching down the circuit layer of the probing device from the top side, the outer support member of the rack bears this touchdown stress. When the probes of the probe holder touching down the electronic components of an IC wafer under test, the center support member of the rack bears the reaction force from the IC wafer. | 01-08-2009 |
| 20100253378 | PROBE FOR HIGH FREQUENCY SIGNAL TRANSMISSION - A probe for high frequency signal transmission includes a metal pin, and a metal line spacedly arranged on and electrically insulated from the metal pin and electrically connected to grounding potential so as to maintain the characteristic impedance of the probe upon transmitting high frequency signal. The maximum diameter of the probe is substantially equal to or smaller than two times of the diameter of the metal pin. Under this circumstance, a big amount of probes can be installed in a probe card for probing a big amount of electronic devices, so that a wafer-level electronic test can be achieved efficiently and rapidly. | 10-07-2010 |
| 20110221462 | PROBE CARD HAVING CONFIGURABLE STRUCTURE FOR EXCHANGING OR SWAPPING ELECTRONIC COMPONENTS FOR IMPEDANCE MATCHING AND IMPEDANCE MATCHING METHOD THEREFORE - A probe card having a configurable structure for exchanging/swapping electronic components for impedance matching and an impedance method therefore are provided. In the probe card, an applied force is exerted on the electronic component so as to make the electronic component electrically connected with at least one conductive contact pad of a supporting unit. The supporting unit is a circuit board or a space transformer. In order to facilitate the exchange or swap of the electronic component, the applied force can be removed. The probe card includes a pressing plate which can be moved between a pressing position and a non-pressing position. The pressing plate has a pressing surface which is contacted with the top end of the electronic component while the pressing plate is in the pressing position. Therefore, the applied force can be generated or removed by changing the positioning of the pressing plate. | 09-15-2011 |
| 20120242360 | High-frequency coupling testing device by coupling effect - Method for transmitting a high-frequency signal by a coupling effect includes receiving a high-frequency signal by a high-frequency circuit and coupling the high-frequency signal to a coupling circuit by the coupling effect to output a high-frequency coupled signal, and adjusting a filter between the coupling circuit and the high-frequency circuit formed by the coupling effect for adjusting transmission frequency of the high-frequency coupled signal; upon when the high-frequency circuit includes a high-frequency metal probe, the coupling circuit comprises a coupling transmission wire. Meanwhile, upon when the high-frequency circuit includes the coupling transmission wire, the coupling circuit includes the high-frequency metal probe. Further, the filter between the coupling circuit and the high-frequency circuit can be adjusted by changing the number of the coupling metal probes surrounding the high-frequency metal probe, or by changing the distances between the coupling metal probes and the high-frequency metal probes. | 09-27-2012 |
| 20140103948 | PROBE CARD HAVING CONFIGURABLE STRUCTURE FOR EXCHANGING OR SWAPPING ELECTRONIC COMPONENTS FOR IMPEDANCE MATCHING - A probe card having a configurable structure for exchanging/swapping electronic components for impedance matching is provided. In the probe card, an applied force is exerted on the electronic component so as to make the electronic component electrically connected with at least one conductive contact pad of a supporting unit. The supporting unit is a circuit board or a space transformer. In order to facilitate the exchange or swap of the electronic component, the applied force can be removed. The probe card includes a pressing plate which can be moved between a pressing position and a non-pressing position. The pressing plate has a pressing surface which is contacted with the top end of the electronic component while the pressing plate is in the pressing position. Therefore, the applied force can be generated or removed by changing the positioning of the pressing plate. | 04-17-2014 |
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| 20120025152 | CONDUCTIVE SILVER POWDER PREPARATION METHOD - A conductive silver powder preparation method includes the following steps: forming a silver salt solution by mixing a silver salt with a DI (De-ionized) water; forming a sodium citrate solution by well-mixing a sodium citrate with the DI water; heating the silver salt solution until maintaining the silver salt solution at a constant temperature of no less than 80° C.; forming a brown solution by adding the sodium citrate solution into the heated silver salt solution; cooling the brown solution to the room temperature for precipitating to form a brown powder; and forming a conductive silver powder by freezing and drying the brown powder. This method simplifies the prior chemical method without usages of toxic reducing agent and additional protective agent, and complies with the requirements of environment, step simplification and economy. | 02-02-2012 |
| 20120027940 | PROTECTION COATINGS, MANUFACTURING METHOD AND USE THEREOF - A protection coating, a manufacturing method and a use thereof are provided. The manufacturing method includes (1) mixing tetraethyl orthosilicate with acrylic silane and evenly stirring at room temperature for 0.5-1.5 hours, so as to obtain an inorganic mixture; (2) mixing the inorganic mixture with deionized water and an organic solvent and continuously stirring at room temperature for 48-72 hours, so as to obtain a clear transparent solution A; (3) preparing a solution of nano-scale silica gel by a sol-gel process; and (4) mixing the solution A with the solution of nano-scale silica gel, adding a predetermined amount of benzoyl peroxide into a mixture of the solution A and the solution of nano-scale silica gel, and evenly stirring at the room temperature for 0.5-1 hour, so as to form a protection coatings of the present invention. The protection coating is applicable on a surface of a plastic product. | 02-02-2012 |
| 20120028028 | MANUFACTURING METHOD OF CONDUCTIVE THIN FILM AND PRODUCT THEREOF - A manufacturing method of conductive thin film includes: (A) preparing tetraethyl orthosilicate (TEOS), 3-methacryloxypropyl-trimethoxysilane and one of or a mixture of vinyl-triethoxysilane (VTEO) and vinyl-trimethoxysilane (VTMO) in a mole ratio of 1:1:1, so as to obtain a silicon-containing reactant; (B) mixing the silicon-containing reactant with a solvent containing water and alcohol, wherein the total quantity of moles of the solvent is two times of that of the silicon-containing reactant; and evenly stirring for at least 12 hours, so as to obtain a semi-finished paint; (C) adding a conductive material in an amount of 3-50 wt % based on a final total weight into the semi-finished paint and evenly stirring, so as to obtain a finished paint; and (D) applying the finished paint to a substrate by coating means, and heating at a temperature of 70-250° C. for 5-60 minutes, so as to form a conductive thin film with continuous pores. | 02-02-2012 |
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| 20080252867 | OVERLAY MARK, AND FABRICATION AND APPLICATION OF THE SAME - An overlay mark is described, including a portion of a lower layer having two x-directional and two y-directional bar-like patterns therein, and two x-directional and two y-directional photoresist bars defined by the lithography process for defining an upper layer and surrounded by the bar-like patterns. At least one of the patterning process for defining the lower layer and the above lithography process includes two exposure steps respectively for defining a first device area and a second device area. When the patterning process includes two exposure steps, one x-directional and one y-directional bar-like patterns are defined simultaneously and the other x-directional and the other y-directional bar-like patterns are defined simultaneously. When the lithography process includes two exposure steps, one x-directional and one y-directional photoresist bars are defined simultaneously and the other x-directional and the other y-directional photoresist bars are defined simultaneously. | 10-16-2008 |
| 20080292974 | EXPOSURE PROCESS AND PHOTOMASK SET USED THEREIN - An exposure process is described, for defining in a photoresist layer a plurality of first patterns having a first pitch and a second pattern between them that is wider than one first pattern. A first exposure step is conducted to the photoresist layer with a first photomask that has a plurality of the first patterns without a second pattern between them, wherein the first patterns on the first photomask have the first pitch only. A second exposure step is conducted to the photoresist layer with a second photomask that has a third pattern narrower than the second pattern at a position corresponding to the second pattern. The exposure dose of the first or second exposure step alone is not sufficient to define any pattern in the photoresist layer. | 11-27-2008 |
| 20100035191 | METHOD FOR PATTERNING MATERIAL LAYER - The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask. | 02-11-2010 |
| 20100053616 | ALIGNMENT MARK AND METHOD OF GETTING POSITION REFERENCE FOR WAFER - An alignment mark on a wafer is described, including at least one dense pattern and at least one block-like pattern adjacent thereto and shown as at least one dark image and at least one bright image adjacent thereto. A method of getting a position reference for a wafer is also described. An above alignment mark is formed. The alignment mark, which is shown as at least one dark image and at least one bright image adjacent thereto that are formed by the at least one dense pattern and the at least one block-like pattern, is then detected. | 03-04-2010 |
| 20110169175 | OVERLAY MARK - An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape. | 07-14-2011 |
| 20110191728 | INTEGRATED CIRCUIT HAVING LINE END CREATED THROUGH USE OF MASK THAT CONTROLS LINE END SHORTENING AND CORNER ROUNDING ARISING FROM PROXIMITY EFFECTS - An integrated circuit that includes a line end created through use of a mask that controls line end shortening and corner rounding arising from proximity effects is provided. The mask includes a main feature having opaque and transmissive areas arranged to reflect a patterned feature of the line end, at least one of an opaque edge or a transmissive edge located at each end of the main feature, wherein the opaque edge has a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge has a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature. | 08-04-2011 |
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| 20140022172 | GESTURE INPUT SYSTEMS AND METHODS - A gesture input system with a two-dimension (2D) image sensor and a processing module is provided. The 2D image sensor obtains a plurality of images of a user. The processing module determines positions of an object and a face of the user in a first image of the plurality of images, and determines an operation area for the user according to the positions of the object and the face. Also, the processing module generates a control command according to the subsequent images to the first image of the user within the operation area. | 01-23-2014 |
| 20140078040 | DUAL-MODE REMOTE CONTROL METHOD - A dual-mode remote control method, adapted to an electronic apparatus having an image sensor, is provided. In the method, the image sensor is used to successively capture a plurality of images. Then, infrared ray (IR) detection and/or gesture detection is determined according to at least one characteristic of the images and performed on the images, so as to obtain an action of at least one target in the images. Finally, a control command corresponding to the action is executed. | 03-20-2014 |
| 20140210704 | GESTURE RECOGNIZING AND CONTROLLING METHOD AND DEVICE THEREOF - A gesture recognizing and controlling method and device thereof are provided. The gesture recognizing and controlling method includes the following steps. First, a pending image having depth information is captured, in which the pending image includes a human form image. The human form image is analyzed so as to obtain hand skeleton information having a first skeleton and a second skeleton. It is determined whether the first skeleton and the second skeleton have an intersection point. If yes, it is determined whether an included angle formed by the first skeleton and the second skeleton is within a predetermined angle range. When the included angle is within the predetermined angle range, a controlling signal is output accordingly. | 07-31-2014 |
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| 20090174463 | Multi-system module having functional substrate - A multi-system module having a functional substrate includes a substrate comprising therein at least one control circuit units, and a plurality of main circuit units provided on one side surface of the substrate. The main circuit units are electrically connected to the control circuit unit, whereby the control circuit unit is used to manage the operation of the main circuit units. Via the above module structure, the substrate can improve the function of controlling multiple systems. | 07-09-2009 |
| 20090192750 | Parallel testing system with shared golden calibration table and method thereof - A parallel testing system with shared golden calibration table includes: a storage unit, multiple testing platforms, and a server. The storage unit is used for storing the golden calibration table, and the testing platforms are used to test a device under test (DUT) respectively by utilizing the golden calibration table. The server is connected to the storage unit and the testing platforms to send the golden calibration table to the testing platforms, and then, to cumulatively record calibration data produced after the testing platforms respectively test the DUTs, so that the server can further perform a weighted arithmetic operation to the calibration data so as to update the golden calibration table. Thereby, the purpose of accelerating the convergence speed of the golden calibration table can be achieved. | 07-30-2009 |
| 20100009501 | Packaging structure, method for manufacturing the same, and method for using the same - A packaging structure applied for a surface mounting process, comprising: a chip module having a packaging surface; and a pre-cured layer formed on the packaging surface of the chip module. As above-mentioned, the structure is employed for protecting the external surface of the wafer. The pre-cured layer is formed on pre-curing a gluing material and the gluing material is uniformly filled with the space between the connecting protrusions on the packaging surface. The pre-cured later is post-curing in a connecting process for mounting the connecting protrusions to the substrate so that the connecting strength is improved. Moreover, the rate of the packaging process is increasing. | 01-14-2010 |
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| 20080258979 | ANTENNA - An antenna is provided comprising a transmission element, a ground element, a first parasitic element, a second parasitic element and a third parasitic element. The transmission element is located on a first plane, wherein the transmission element is T shaped, and comprises a first transmission portion and a second transmission portion and the second transmission portion is perpendicular to the first transmission portion and connected to an end thereof. The ground element is located on a second plane parallel to the first plane. The first parasitic element, the second parasitic element and the third parasitic element are connected to the ground element and located on the second plane. | 10-23-2008 |
| 20120176768 | LED Light Tube - An LED (Light-Emitting Diode) light tube includes a transparent tube, a phosphor layer and a base board. The phosphor layer is coated on a surface of the transparent tube, wherein a thickness of the phosphor layer is 10-100 μm. The base board is arranged inside the transparent tube for carrying a plurality of LEDs (Light-Emitting Diodes), wherein the length between the base board and the top of the transparent tube is H, and the distance between every two adjacent LEDs is P, and H/P is not smaller than 0.134 and H is 9.5-38 mm. | 07-12-2012 |
| 20120320562 | LED LIGHTING DEVICE - An LED (Light-Emitting Diode) lighting device is provided. The LED lighting device comprises an LED module, a lamp cover, and a phosphor layer. The LED module comprises a circuit board comprising a driving circuit and a plurality of LEDs mounted on the circuit board and driven by the driving circuit so as to emit light of 300-700 nm in wavelength. The lamp cover is configured to shield the LED module. The phosphor layer is coated on an inner surface of the lamp cover towards the LED module and configured to transform the light of 300-700 nm in wavelength to a luminary light of 400-700 nm in wavelength. | 12-20-2012 |
| 20120326184 | LED LIGHTING FIXTURE AND THE MANUFACTURING METHOD THEREOF - A LED (Light-Emitting Diode) lighting fixture and a manufacturing method thereof are disclosed. The LED lighting fixture comprises a LED module generating light at a wavelength range of 300-700 nm, a lamp cover shielding the LED module, and a phosphor layer. The phosphor layer which is coated on an inner surface towards the LED module comprises at least two types of phosphor mixed at a default ratio for transforming the light of 300-700 nm in wavelength to luminary light in the wavelength range of 400-700 nm. | 12-27-2012 |
| 20140268877 | LUMINOUS ELEMENT, BAR-TYPE LUMINOUS ELEMENT AND APPLICATIONS THEREOF - A luminous element includes a heat dissipation plate, a body, a plurality of LED chips, a first connector and a second connector. The heat dissipation plate includes a die-bonding area and a heat dissipation area opposite to the die-bonding area. The body surrounds the heat dissipation plate, and includes a first body surface and a second body surface opposite to the first body surface. The first body surface includes a concave part exposing the die-bonding area. The second body surface includes an opening exposing the heat dissipation area. The LED chips are mounted on the die-bonding area. The first and the second connectors are disposed on the body, and they can be pluggably connected to an external power source or other connectors. The LED chips are connected to the electrical input terminals in the first and the second connectors. | 09-18-2014 |
| 20150124476 | LIGHTING APPARATUS AND WAVELENGTH CONVERTING APPARATUS THEREOF - A lighting apparatus includes a wavelength converting apparatus. The wavelength converting apparatus includes a hollow tube and a wavelength converting material. The hollow tube has an accommodating chamber. The wavelength converting material is positioned in the accommodating chamber. | 05-07-2015 |
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| 20120229963 | ELECTRONIC APPARATUS WITH EMI SHIELDING STRUCTURE - An electronic apparatus includes a case having an opening, and at least one retaining section is adjacent to the opening. At least one retaining pin is arranged in each of the at least one retaining section. The electronic apparatus further includes a cover to cover the opening. The cover includes at least one fixing section engaging with the at least one retaining section. A receiving chamber is arranged in each of the at least one fixing section to receive a clamp section of a resilient piece clamping the at least one retaining pin. The resilient piece is movable when the retaining pin is clamped by the clamp section arranged in the receiving chamber. | 09-13-2012 |
| 20130163183 | HARD DISK CARRIER - A hard disk carrier includes a receiving frame, a plane, and an electromagnetic shielding module. The receiving frame is used to hold a hard disk. The electromagnetic shielding module is mounted between the receiving frame and the plane. The electromagnetic shielding module defines a plurality of openings through the opposite ends. The edge of each opening extending outward from the surface and forming a cylinder peripheral wall, each opening and the peripheral wall corresponding to the opening forming a waveguide. | 06-27-2013 |
| 20130277010 | HEAT DISSIPATING APPARATUS WITH AIR DUCT - A heat dissipating apparatus in an electrical device includes a air duct. The air duct includes an air inlet and an air outlet. A plurality of ventilation members are attached to the air inlet and the air outlet thereof. Each ventilation member defines a number of ventilation holes of a certain size calculated to keep EMI out. A coated layer formed on an inner surface of the air duct to shield electromagnetic waves which may be generated by the electrical components of the device. | 10-24-2013 |
| 20130279123 | ELECTRONIC DEVICE WITH DETACHABLE MODULE - An electronic device includes a chassis, a detachable module received in the chassis, and a latching member. The detachable module includes an end plate defining an opening. One end of the latching member is fixed in the detachable module, and the other end of the latching member extends out of the detachable module through the opening. The detachable module defines a through hole. The chassis defines a latching hole corresponding to the through hole. A latching block protrudes out from one side of the latching member and extends through the through hole to engage in the latching hole. A shielding piece comes across to block and shield the opening. | 10-24-2013 |
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| 20110075024 | Photographic Device and Holder Thereof - A holder is disclosed, wherein the holder is situated on a circuit board and is used for connecting with an electronic component. The holder comprises an upper surface, a lower surface, and an opening. The upper surface comprises a recess used for laying a flat component, wherein the recess comprises at least one rough area; the lower surface comprises a protruding edge, wherein the protruding edge is connected with the circuit board with glue, and the protruding side and the circuit board delimit a space; and the opening penetrates the upper surface and the lower surface, whereby the gas generated from heating the glue will accumulate in the enclosed space, and the gas will then escape through the opening and out through at least one of the rough areas. | 03-31-2011 |
| 20130341757 | Masking-Less Fuse Formation with Oxide Remaining - The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface. | 12-26-2013 |
| 20150051860 | AUTOMATIC OPTICAL APPEARANCE INSPECTION BY LINE SCAN APPARATUS - A method of inspecting a structure of a device and a system for doing the same is described. The method includes generating a sample image of a device having a structure to be inspected; identifying a plurality of features of the sample image; comparing the plurality of features to a corresponding plurality of features of a reference image; and locating features in the sample image that deviate from corresponding features of the reference image. The generating step includes moving the device, a detector array or both, relative to one another, wherein the detector array is configured to generate a line of data representing light reflected from the device, and assembling lines of data from the detector array to generate a sample image. | 02-19-2015 |
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| 20130016796 | SIGNAL MODULATOR AND SIGNAL MODULATING METHODAANM Sun; Chih-HaoAACI New Taipei CityAACO TWAAGP Sun; Chih-Hao New Taipei City TWAANM Yu; Chi-YaoAACI Hsinchu CountyAACO TWAAGP Yu; Chi-Yao Hsinchu County TW - A signal modulator includes: a modulating circuit; a first signal trace block arranged to conduct a first in-phase oscillating signal to the modulating circuit, and conduct a first quadrature-phase oscillating signal to the modulating circuit; and a second signal trace block arranged to conduct a second in-phase oscillating signal to the modulating circuit, and conduct a second quadrature-phase oscillating signal to the modulating circuit, and a phase difference caused by the first signal trace block substantially equals a phase difference caused by the second signal trace block. | 01-17-2013 |
| 20130142274 | SLICED TRANSMITTER FRONT-END - An embodiment of the invention provides a sliced transmitter front-end (TX FE). The sliced TX FE includes first TX FE slices and a second TX FE slice that are connected in parallel. As a whole the first TX FE slices contributes a high-gain section to a superimposed gain range of the sliced TX FE. The second TX FE slice has a gain range that constitutes a low-gain section of the superimposed gain range of the sliced TX FE. A minimum gain of the gain range of the second TX FE slice is smaller than a minimum gain of the high-gain section. | 06-06-2013 |
| 20140086360 | TRANSMITTER SUPPORTING TWO MODES - A transmitter includes a first channel and a second channel. The first channel includes a first mixer, and is used for processing a first input signal to generate a first output signal; the second channel includes a second mixer, where the second channel does not receive any input signal. When the transmitter is operated under a first mode, both the first mixer and the second mixer receive oscillation signals. | 03-27-2014 |
| 20150156053 | SIGNAL MODULATOR AND SIGNAL MODULATING METHOD - A signal modulator includes: a modulating circuit; a first signal trace block arranged to conduct a first in-phase oscillating signal to the modulating circuit, and conduct a first quadrature-phase oscillating signal to the modulating circuit; and a second signal trace block arranged to conduct a second in-phase oscillating signal to the modulating circuit, and conduct a second quadrature-phase oscillating signal to the modulating circuit, and a phase difference of the first in-phase oscillating signal caused by the first signal trace block substantially equals a phase difference of the second quadrature-phase oscillating signal caused by the second signal trace block, a second quadrature-phase oscillating signal to the modulating circuit, and a phase difference of the second in-phase oscillating signal caused by the second signal trace block substantially equals a phase difference of the first quadrature-phase oscillating signal caused by the first signal trace block. | 06-04-2015 |
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| 20130323899 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 12-05-2013 |
| 20140312432 | SEMICONDUCTOR ARRANGEMENT WITH SUBSTRATE ISOLATION - One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance. | 10-23-2014 |
| 20140353731 | Tuning Strain in Semiconductor Devices - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. | 12-04-2014 |
| 20150021697 | Thermally Tuning Strain in Semiconductor Devices - A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric. | 01-22-2015 |
| 20150028426 | BURIED SIGE OXIDE FINFET SCHEME FOR DEVICE ENHANCEMENT - The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions. | 01-29-2015 |
| 20150048442 | SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS - A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance. | 02-19-2015 |
| 20150048453 | FinFETs and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region. | 02-19-2015 |
| 20150054030 | Defect-Free SiGe Source/Drain Formation by Epitaxy-Free Process - MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance. | 02-26-2015 |
| 20150144999 | Structure and Method For FinFET Device With Buried Sige Oxide - The present disclosure provides a semiconductor device that includes a substrate of a first semiconductor material; a fin feature having a first portion, a second portion and a third portion stacked on the substrate; an isolation feature formed on the substrate and disposed on sides of the fin feature; semiconductor oxide features including a second semiconductor material, disposed on recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extended into and filling in the dented voids. The first and third portions include the first semiconductor material having a first lattice constant. The second portion includes the second semiconductor material having a second lattice constant different from the first lattice constant. | 05-28-2015 |
| 20150187944 | Semiconductor Liner of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure comprises a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant. | 07-02-2015 |
| 20150194503 | Fin Structure of Semiconductor Device - Semiconductor devices and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacturing a semiconductor device comprises forming a fin structure over a substrate. The fin structure may comprise a lower portion protruding from a major surface of the substrate, an upper portion, and a middle portion between the lower portion and the upper portion, wherein the lower portion and the middle portion differ in composition. The method may further include forming an isolation structure surrounding the fin structure and oxidizing the fin structure. The oxidizing may form a pair of notches extending from sidewalls of the fin structure into the middle portion of the fin structure. | 07-09-2015 |
| 20150200252 | Fin Structure of Semiconductor Device - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow. | 07-16-2015 |
| 20150200300 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow. | 07-16-2015 |
| 20150214333 | Tuning Strain in Semiconductor Devices - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. | 07-30-2015 |
| 20150262876 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area. | 09-17-2015 |
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| 20120235026 | IMAGE SENSOR PIXEL AND DRIVING METHOD THEREOF - An image sensor pixel and a driving method thereof are provided. The image sensor pixel comprises a photodiode, a sensing capacitor, a static transistor and a dynamic transistor. A first terminal of the photodiode is coupled to a bias line. A control terminal of the static transistor is coupled to a static gate line, and a first terminal of the static transistor is coupled to a first terminal of the sensing capacitor and a second terminal of the photodiode. A control terminal of the dynamic transistor is coupled to a dynamic gate line, and a first terminal of the dynamic transistor is coupled to a second terminal of the sensing capacitor. | 09-20-2012 |
| 20140145085 | FLAT PANEL X-RAY DETECTOR - The present invention relates to a flat panel X-ray detector, which comprises a thin film transistor (TFT) substrate; a photoelectric detecting layer, which is disposed on and electrically connected with the TFT substrate, wherein the photoelectric detecting layer comprises a plurality of photoelectric detecting units and a plurality of light absorption units, and the light absorption unit is disposed between spaces adjacent to the photoelectric detecting unit; a Scintillation layer, which is disposed on the photoelectric detecting layer; and a reflective layer, which is disposed on the Scintillation layer. | 05-29-2014 |
| 20140151684 | X-RAY DETECTOR - An X-ray detector including a thin film transistor (TFT) substrate and a photo-diode array layer is disclosed. Each thin film transistor in the TFT substrate includes: a substrate; a gate-electrode on the substrate; a gate insulating layer on the gate-electrode; a semiconductor layer on the gate insulating layer, wherein a portion of the semiconductor layer covers the gate-electrode; an etching stop layer covering the semiconductor layer; a source-electrode and a drain-electrode respectively disposed on the etching stop layer, wherein the source-electrode and the drain-electrode are respectively electrically connected to the semiconductor layer through conductive via-holes each having a base portion at the semiconductor layer, and at least one of the projection areas of the base portions vertically projected on the substrate has a non-overlapping region beyond the projection area of the gate-electrode vertically projected on the substrate; and a passivation layer covering the source-electrode and the drain-electrode. | 06-05-2014 |
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| 20140210837 | Image Processing Device, Image Processing Method, and Liquid Crystal Display Incorporated with Image Processing Device - The present invention provides an image processing device, including a buffering unit, a minifying unit, a synchronous dynamic random access memory (SDRAM), an overdriving unit, a comparing unit, a restoring unit, and an output controlling unit. The present invention further provides an image processing method and a liquid crystal display incorporated with the image processing device. The image processing device, the image processing method, and the liquid crystal display incorporated with the image processing device will not only directly perform the overdrive-processing of an input high-resolution image, but will also, on the one hand caches an input high-resolution image by the buffering unit, and on the other hand minifies an input high-resolution image. As a result, the image data is already reduced when the overdrive-processing performs, and the consumption of the space of the SDRAM is also accordingly reduced. For the input of a high-resolution image, there is no need to increase the amount of the SDRAM anymore, and it is easier to control the overall cost. During output, a static image is directly output, and a dynamic image is output through the overdrive-processing and the restoration of original resolution to maintain the quality of the image. | 07-31-2014 |
| 20150153605 | Voltage Compensation Circuit of Gate Driver and Method Thereof and Liquid Crystal Display Device - A voltage compensation circuit includes a voltage detection unit, a digital comparison correction unit, and a voltage adjustment unit. The voltage detection unit detects input voltage of the gate driver and conducts the input voltage to the digital comparison correction unit. The digital comparison correction unit compares the input voltage with reference voltage supplied by a controller for generating a correction controlling signal and conducting the correction controlling signal to the voltage adjustment unit. The voltage adjustment unit adjusts the input voltage and outputs a target voltage according to the correction controlling signal. The gate driver conducts the target voltage to an LCD panel. In this way, a scanning voltage conducted to a gate driver is adjusted. Therefore, a voltage drop will not exist between output voltages of different gate drivers, not only preventing mura from occurring in the LCD panel but also improving display quality of the LCD panel. | 06-04-2015 |
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| 20080225243 | PROJECTION APPARATUS - A projection apparatus including a projection body and at least one adjusting leg is provided. The projection body has a casing, and the bottom of the casing has at least one accommodating cave. The adjusting leg includes a supporter and a pivoting rod. The supporter has a supporting portion and a screw connected to the supporting portion, and the projection body is capable of being supported on a surface by the supporting portion. The pivoting rod is pivoted to the casing and has a threaded hole, and the screw is screwed into the threaded hole. The pivoting rod is capable of being rotated along an axis of the pivoting rod to drive the supporter to rotate, so as to accommodate the supporting portion in the accommodating cave. | 09-18-2008 |
| 20080266236 | Driving method of liquid crystal display device having dynamic backlight control unit - A dynamic control method for controlling backlight module of liquid crystal display (LCD) comprises steps of: receiving a frame data which is transferred to the LCD and consists a plurality of raw grayscale level; processing a statistical analysis for distribution of the plurality of raw grayscale level; and transferring a plurality of corrected grayscale level which is resulted from the statistical analysis corresponding to the raw grayscale level to the backlight control unit and a data modification simultaneously, wherein the backlight control unit uses the plurality of corrected grayscale level to modify brightness of backlight module and the data modification uses the plurality of corrected grayscale level to compare with the plurality of raw grayscale level for accurate display performance, so that the electrical power consumption is reduced and image quality is enhanced. | 10-30-2008 |
| 20090059186 | LAMP HOLDER OF A PROJECTION APPARATUS AND FABRICATION THEREOF - A method for forming a lamp holder. The lamp holder is applied in a projection apparatus. First, the lamp holder comprising metal is provided. An insulating layer is formed on one surface of the lamp holder to insulate the lamp holder from another element of the projection apparatus. | 03-05-2009 |
| 20090103057 | AUTOMATIC IRIS DIAPHRAGM MODULE - An automatic iris diaphragm module is adapted to a projector having a casing, and is capable of adjusting a size of luminous flux of a light source of the projector. The automatic iris diaphragm module is provided with a chassis, a fixed mask, a movable mask, a drive rack, and a motor. The chassis is fixed on the casing. The fixed mask is fixed on the chassis and has an opening. The movable mask is slidably disposed on the fixed mask. The drive rack is fixed on the movable mask. The motor is fixed on the chassis and has a driving gear engaging with the drive rack for driving the drive rack to make the movable mask slide relative to the fixed mask, for adjusting the size of the luminous flux of the light source through the opening. | 04-23-2009 |
