Patent application number | Description | Published |
20100134234 | SHIFT REGISTER APPARATUS - A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof. | 06-03-2010 |
20100302178 | TOUCH PANEL DISPLAY - A touch panel display including a first substrate, a second substrate, a display medium and a touch device is provided. The first substrate has a display area and a peripheral area. The first substrate has a pixel array in the display area and at least one integrated driving circuit in the peripheral area. The integrated driving circuit is electrically connected to the pixel array. The second substrate is disposed above the first substrate to cover the integrated driving circuit and the pixel array. The display medium is disposed on the pixel array and located between the first substrate and the second substrate. The touch device is disposed on the second substrate, and has a sensor element and a wiring element connected to the sensor element. The sensor element is located above the pixel array and the wiring element is located above at least a portion of the integrated driving circuit. | 12-02-2010 |
20110102310 | SHIFT REGISTER WITH IMAGE RETENTION RELEASE AND METHOD FOR IMAGE RETENTION RELEASE - A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high. | 05-05-2011 |
20130215063 | TOUCH PANEL DISPLAY - A touch panel display including a first substrate, a second substrate, a display medium and a touch device is provided. The first substrate has a display area and a peripheral area. The first substrate has a pixel array in the display area and at least one integrated driving circuit in the peripheral area. The integrated driving circuit is electrically connected to the pixel array. The second substrate is disposed above the first substrate to cover the integrated driving circuit and the pixel array. The display medium is disposed on the pixel array and located between the first substrate and the second substrate. The touch device is disposed on the second substrate, and has a sensor element and a wiring element connected to the sensor element. The sensor element is located above the pixel array and the wiring element is located above at least a portion of the integrated driving circuit. | 08-22-2013 |
Patent application number | Description | Published |
20080308873 | Semiconductor device with discontinuous CESL structure - A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode. | 12-18-2008 |
20100038692 | Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors - An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode. | 02-18-2010 |
20100231497 | DISPLAY DEVICE PROVIDING BI-DIRECTIONAL VOLTAGE STABILIZATION - An LCD device includes a plurality of gate lines and a plurality of shift register units for driving corresponding gate lines. Each shift register unit includes a first circuit and a second circuit. The first circuit, disposed on a first side of a corresponding gate line, includes a pulse generator and a first transistor having a first W/L ratio. The pulse generator provides a driving signal according to the voltage obtained at a node, while the first transistor maintains the voltage level of the node. The second circuit, disposed on a second side of the corresponding gate line, includes a second transistor having a second W/L ratio. The second transistor maintains the voltage level of the driving signal from the second side of the corresponding gate line. The first W/L ratio is smaller than the second W/L ratio, and the first circuit occupies larger space than the second circuit. | 09-16-2010 |
20110085098 | ARRAY SUBSTRATE AND FLAT DISPLAY DEVICE - A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line. | 04-14-2011 |
20130034946 | Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors - An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode. | 02-07-2013 |
Patent application number | Description | Published |
20090039433 | SEMICONDUCTOR DEVICE WITH HIGH-K/DUAL METAL GATE - An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions. | 02-12-2009 |
20100044803 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 02-25-2010 |
20100052072 | DUAL GATE STRUCTURE ON A SAME CHIP FOR HIGH-K METAL GATE TECHNOLOGY - A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region. | 03-04-2010 |
20100109088 | BALANCE STEP-HEIGHT SELECTIVE BI-CHANNEL STRUCTURE ON HKMG DEVICES - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 05-06-2010 |
20110278646 | Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 11-17-2011 |
20120225529 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 09-06-2012 |
20150372637 | SOLAR MODULE FRAME - A solar module frame includes two first borders and two second borders. At least one first border includes a first segment and a second segment, where one end of the first segment is connected to one end of the second border, and one end of the second segment is connected to one end of the other second border. The solar module frame includes at least one connection component. One end of the connection component is connected to the other end of the first segment, and the other end of the connection component is connected to the other end of the second segment. Each of the first segment, the second segment, and the connection component includes an external wall, a support wall, a first clamping wall, and a second clamping wall. Each of the first segment and the second segment includes an internal wall. | 12-24-2015 |
Patent application number | Description | Published |
20090116266 | PARALLELED POWER CONDITIONING SYSTEM WITH CIRCULATING CURRENT FILTER - This present invention relates to a paralleled power conditioning system with circulating current filter, comprising: an input terminal for receiving a input power; a plurality of power conditioning units; and a load. Each power conditioning unit includes: a DC/DC converter coupled to the input for receiving the input power so as to convert the input power to a DC voltage; a DC/AC inverter coupled to the DC/DC converter for converting the DC voltage to a AC voltage; and a filter coupled to the DC/AC inverter for eliminating the noise generated by the AC voltage and the circulating current among the plurality of power conditioning units so as to generate a filter voltage. The load is connected to the plurality of power conditioning units. The plurality of power conditioning units are connected in parallel to the load. | 05-07-2009 |
20110245626 | System for human physical parameters examination - A system for detecting and recording a user's physical parameters, an interactive TV receiver connected to an information network system for receiving physical parameters data detected by the physical parameter scanner and transmitting the data to a rear end server and database through the information network system for enabling a remote user, remote hospital or remote pharmacy to trace patient's physical conditions and to provide the necessary medication services. | 10-06-2011 |
20130262562 | DATA COMMUNICATION MANAGING SYSTEM AND METHOD THEREOF - The present invention provides a data communication managing system. The system includes a first network segment client, a second network segment client, and a center unit. The center unit includes a manage unit and transmit data with the first network segment client and the second network segment client, respectively. The manage unit includes a transmission management part which is used to disallow the data transmission between the first network segment client and the second network segment client. | 10-03-2013 |
20140307164 | METHOD AND DEVICE FOR SIGNAL CONCATENATION - The present invention discloses a method for signal concatenation. The method inputs signals from other signal device to a first signal device and outputs the signals from the first signal device after processed by the first signal device, comprises the steps of: establishing a connection between the first signal device and the other signal device; inputting the signals outputting from the other signal device to the first signal device; processing the input signals by the first signal device; and outputting the processed signals to an external device by the first signal device. | 10-16-2014 |
Patent application number | Description | Published |
20120043926 | Power Management Device, Power Management Method and Portable Electronic Device - A power management device for a portable electronic device includes a sensing unit, coupled between a power supply and a system circuit of the portable electronic device, for sensing current outputted from the power supply to the system circuit, to generate a sensing signal, and a control unit, coupled between the sensing unit and a charger module of the portable electronic device, for indicating the charger module to stop charging when the sensing signal indicates that current outputted from the power supply to the system circuit is greater than a predetermined value. | 02-23-2012 |
20130221902 | CHARGING DEVICE AND CHARGING METHOD - A charging device including a charging circuit, a voltage detection circuit, and a keyboard controller is provided. The charging circuit receives a charging power source, and produces a battery-charging power source at a first node by the charging power source to charge a battery. The voltage detection circuit detects a voltage at the first node, and produces a voltage detection result. The keyboard controller determines whether the voltage at the first node is less than a predetermined voltage according to the voltage detection result, and determines whether a predetermined condition has been satisfied, wherein the predetermined condition includes the voltage at the first node being less than the predetermined voltage, and the keyboard controller is arranged to force the charging circuit to stop producing the battery-charging power source at the first node when the predetermined condition has been satisfied. | 08-29-2013 |
20130300216 | Power Saving Method and Power Saving Circuit Thereof - A power saving circuit for an electronic device is disclosed. The power saving circuit includes a direct-current (DC) power supply, a sensing unit, and a control unit. The DC power supply is used for providing a DC current. The sensing unit, coupled to the DC power supply, is used for detecting the DC current and operating to generate a voltage signal according to the DC current. The control unit, coupled to the sensing unit, is used for determining whether a system circuit of the electronic device has a light load or a heavy load and generating an enable signal. | 11-14-2013 |
20140215203 | PROTECTION DEVICE, PROTECTION METHOD AND ELECTRONIC SYSTEM THEREOF - A protection device for an electronic system includes a detecting module, coupled between a power supply device and a computing device of the electronic system for generating a current instruction signal according to the current value of a supply current transmitted from the power supply device to the computing device; a determining module, coupled to the detecting module for generating a control signal according to the current instruction signal and at least one threshold; and a performance adjusting module, coupled to the determining module and the computing device for adjusting the performance of the computing device according to the control signal. | 07-31-2014 |
20150134980 | POWER SUPPLYING CIRCUIT, POWER SUPPLYING SYSTEM AND POWER SUPPLYING METHOD - A power supplying circuit adapted for receiving an output from a power adapter and supplying power to a battery unit and a system load is provided. The power supplying circuit includes a charger unit, a switching unit, and a voltage regulating unit. The charger unit receives a first supplying voltage from the power adapter through a power terminal and charges the battery unit. The switching unit is coupled to the power terminal and the charger unit. The switch unit is configured for receiving the first supplying voltage and a second supplying voltage from the charger unit. The voltage regulating unit is coupled to the switching unit and configured for powering the system load. The switching unit supplies the first supplying voltage to the voltage regulating unit under heavy load condition. The switching unit supplies the second supplying voltage to the voltage regulating unit under light load condition. | 05-14-2015 |
Patent application number | Description | Published |
20130043930 | CHARGE PUMP - A charge pump exhibiting a voltage compensation function is provided. The charge pump includes: a first current generator, a first semiconductor device, a second current generator, a second semiconductor device, and a voltage regulator. The voltage regulator dynamically adjusts a voltage level at the gate of the first or second semiconductor device so as to adjust a first current or a second current outputted to a current output node. In addition, the voltage regulator provides a bias voltage at the current output node when both the first and second semiconductor devices are turned off. | 02-21-2013 |
20130069711 | CHARGE PUMP SYSTEM CAPABLE OF STABILIZING AN OUTPUT VOLTAGE - A charge pump system includes a charge pump, a ring oscillator, a comparing circuit and a discharge circuit. When an output voltage of the charge pump is relatively low, the comparing circuit turns on the ring oscillator to make the ring oscillator provide an oscillation output to the charge pump to raise the output voltage of the charge pump. When the output voltage of the charge pump is relatively high, the comparing circuit turns off the ring oscillator to stop the ring oscillator from providing the oscillation output to the charge pump, the comparing circuit also makes the discharge circuit provide a discharge path to the charge pump to quickly reduce the output voltage of the charge pump. | 03-21-2013 |
20130099852 | CHARGE PUMP CIRCUIT WITH LOW CLOCK FEED-THROUGH - A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit. | 04-25-2013 |
Patent application number | Description | Published |
20160015371 | Sampling Apparatus - A sampling apparatus contains: a tubular member, a pressing mechanism, a forcing member, and a movable sampling member. The tubular member includes an inner thread section, an orifice, a stepped shoulder, a first fixing hole, and a second fixing hole. The pressing mechanism includes a press member, a driving member, a resilient element, and an elastic hook. The driving member includes an inserting segment, an aperture, a retaining slot, and a receiving groove, and two ends of the resilient element abut against the driving member and the forcing member. The cylindrical member includes an outer thread section and two opposite positioning recesses. The forcing member includes a needle and two opposite locating stems. The movable sampling member includes a hollowly lower side, a hollow affixing mount, a hollow tool, and a blade. | 01-21-2016 |