Patent application number | Description | Published |
20130105979 | Package on Package Devices and Methods of Packaging Semiconductor Dies | 05-02-2013 |
20130168856 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die. | 07-04-2013 |
20130256914 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - The described embodiments of forming bonding structures for package on package involves removing a portion of connectors and molding compound of the lower package. The described bonding mechanisms enable easier placement and alignment of connectors of an upper package to with connector of a lower package. As a result, the process window of the bonding process is wider. In addition, the bonding structures have smoother join profile and planar joint plane. As a result, the bonding structures are less likely to crack and also are less likely to crack. Both the yield and the form factor of the package on package structure are improved. | 10-03-2013 |
20130270705 | Semiconductor Device Packages and Methods - Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate. | 10-17-2013 |
20130299984 | Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging - Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress. | 11-14-2013 |
20140001612 | Multiple Die Packaging Interposer Structure and Method | 01-02-2014 |
20140015086 | Interconnect Structure for CIS Flip-Chip Bonding and Methods for Forming the Same - A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity. | 01-16-2014 |
20140021605 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint. | 01-23-2014 |
20140041918 | Looped Interconnect Structure - Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder. | 02-13-2014 |
20140042621 | Package on Package Devices and Methods of Forming Same - An embodiment is a package-on-package (PoP) device comprising a first package on a first substrate and a second package over the first package. A plurality of wire sticks disposed between the first package and the second package and the plurality of wire sticks couple the first package to the second package. Each of the plurality of wire sticks comprise a conductive wire of a first height affixed to a bond pad on the first substrate and each of the plurality of wire sticks is embedded in a solder joint. | 02-13-2014 |
20140042623 | SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME - An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die. | 02-13-2014 |
20140084459 | Multiple Die Packaging Interposer Structure and Method - System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly. | 03-27-2014 |
20140124916 | Molded Underfilling for Package on Package Devices - Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall. | 05-08-2014 |
20140183725 | POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump. | 07-03-2014 |
20140197547 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector. | 07-17-2014 |
20140206140 | Method of Forming Wafer-Level Molded Structure for Package Assembly - A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units. | 07-24-2014 |
20140252596 | Bump-on-Trace (BOT) Structures and Methods for Forming the Same - An integrated circuit structure includes a package component, which includes a dielectric layer and a metal trace over and in contact with the dielectric layer. The dielectric layer includes a first dielectric material and a second dielectric material in the first dielectric material. The first dielectric material is a flowable and curable material. The second dielectric material comprises a functional group selected from the group consisting essentially of (—C—N—), (—C—O—), (—N—C═O), and combinations thereof. | 09-11-2014 |
20140252609 | Package-on-Package Structure and Methods for Forming the Same - A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material. | 09-11-2014 |
20150056737 | Interconnect Structure for CIS Flip-Chip Bonding and Methods for Forming the Same - A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity. | 02-26-2015 |
20150187743 | WAFER LEVEL PACKAGE STRUCTURE AND METHOD OF FORMING SAME - An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure. | 07-02-2015 |
20150206865 | Integrated Circuit Package and Methods of Forming Same - An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip. | 07-23-2015 |
20150206866 | Semiconductor Package and Methods of Forming Same - An embodiment package-on-package (PoP) device includes a fan-out structure, one or more memory chips, and a plurality of connectors bonding the one or more memory chips to the fan-out structure. The fan-out structure includes a logic chip, a molding compound encircling the logic chip, and a plurality of conductive pillars extending through the molding compound. | 07-23-2015 |
20150214181 | METHODS FOR FORMING A SEMICONDUCTOR DEVICE PACKAGE - A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector. | 07-30-2015 |
20150214191 | Packages with Stacked Dies and Methods of Forming the Same - A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate. | 07-30-2015 |
20150228587 | Concentric Bump Design for the Alignment in Die Stacking - An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other. | 08-13-2015 |
20150235936 | SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME - An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies. | 08-20-2015 |
20150235989 | SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME - An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate. | 08-20-2015 |
20150235990 | SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME - An embodiment device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity. | 08-20-2015 |
20150235993 | Thermal Performance Structure for Semiconductor Packages and Method of Forming Same - An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole. | 08-20-2015 |
20150318271 | Method of Forming Wafer-Level Molded Structure for Package Assembly - A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units. | 11-05-2015 |
20150364344 | Integrated Circuit Packages and Methods of Forming Same - Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die. | 12-17-2015 |
20150364386 | Stacked Semiconductor Devices and Methods of Forming Same - Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces. | 12-17-2015 |
20150364436 | Integrated Circuit Packages and Methods of Forming Same - Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a packaged semiconductor device. An encapsulant is formed over the IC dies and between the neighboring IC dies. The encapsulant and the IC dies are planarized to expose contacts on top surfaces of the IC dies, and redistribution layers (RDLs) are formed over the planarized encapsulant and the planarized IC dies. Openings are formed in a topmost dielectric layer of the RDLs to expose interconnects in the RDL, and a conductive seed layer is formed over the RDL and in the openings. Connectors of a first type and connectors of a second type are formed over the seed layer in the openings. The packaged semiconductor device is diced into individual IC packages. | 12-17-2015 |
20160056087 | PACKAGE-ON-PACKAGE STRUCTURE WITH ORGANIC INTERPOSER - A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands. | 02-25-2016 |
20160104668 | POP JOINT THROUGH INTERPOSER - A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, with the first solder region in contact with a bottom end of the conductive pipe, and a through-opening in a center region of the interposer. | 04-14-2016 |
Patent application number | Description | Published |
20110024804 | METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SIGE STRESSOR - A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation. | 02-03-2011 |
20110227188 | INTEGRATED CIRCUITS INCLUDING DUMMY STRUCTURES AND METHODS OF FORMING THE SAME - An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures. | 09-22-2011 |
20120124528 | METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements are added to a portion of the space between the adjacent active regions to connect the mandrel ends from one active region to another active region. | 05-17-2012 |
20120126326 | DEVICE AND METHOD FOR FORMING FINS IN INTEGRATED CIRCUITRY - A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures. | 05-24-2012 |
20120126375 | METHOD FOR FORMING METROLOGY STRUCTURES FROM FINS IN INTEGRATED CIRCUITRY - A method for forming a plurality of fins on a semiconductor substrate includes depositing a spacer layer to fill in gaps between the plurality of fins, the fins comprising a first material and the spacer layer comprising a second material. A first area is defined where the fins need to be broadened and a second area is defined where the fins do not need to be broadened. The method also includes patterning the spacer layer to remove spacers in the first area where the fins need to be broadened and applying an epitaxy process at a predetermined rate to grow a layer of the first material on fins in the first area. The spacer layer is removed in the second area where the fins do not need broadening. | 05-24-2012 |
20140013288 | METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS - A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions. | 01-09-2014 |
20140091362 | INTEGRATED CIRCUIT TRANSISTOR STRUCTURE WITH HIGH GERMANIUM CONCENTRATION SiGe STRESSOR - An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more. | 04-03-2014 |
20140239418 | Semiconductor Dielectric Interface and Gate Stack - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer. | 08-28-2014 |
20140331193 | METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS - A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to the first direction. The method further includes defining a second plurality of mandrels in a second active region of the first layout. Each mandrel of the second plurality of mandrels extends in the first direction and being spaced apart in the second direction. An edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing. The method further includes connecting, using a layout generator, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels. | 11-06-2014 |
20140353771 | Semiconductor Dielectric Interface and Gate Stack - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer. | 12-04-2014 |
20150129938 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region. | 05-14-2015 |
20150318213 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region. | 11-05-2015 |
20150318214 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICTAING THE SAME - The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer. | 11-05-2015 |
20160071966 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region. | 03-10-2016 |
20160079358 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer. | 03-17-2016 |
Patent application number | Description | Published |
20140209800 | NON-DISPERSIVE INFRARED GAS DETECTOR, AND METHOD OF STABILIZING INFRARED EMISSION OF AN INCANDESCENT LAMP - An NDIR gas detector includes a photodetector for detecting a portion of stray visible light emitted from an incandescent lamp so as to generate an induced electrical signal, which is compared with a preset reference signal associated with a predetermined constant level of the stray visible light corresponding to a constant temperature of the lamp so as to obtain a level difference between the induced electrical signal and the reference signal. Electrical power supplied to the lamp is repeatedly regulated based on the level difference until the induced electrical signal and the reference signal have the same level, thereby stabilizing IR emission of the lamp in response to the lamp being kept at the constant temperature. | 07-31-2014 |
20150069467 | DELTA DOPING LAYER IN MOSFET SOURCE/DRAIN REGION - A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer. | 03-12-2015 |
20150102287 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. | 04-16-2015 |
20150108550 | TRANSISTOR AND METHOD FOR FORMING THE SAME - A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel. | 04-23-2015 |
20150129981 | SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel. | 05-14-2015 |
20150228721 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 08-13-2015 |
20150255306 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. | 09-10-2015 |
20150263094 | SEMICONDUCTOR DEVICES WITH CORE-SHELL STRUCTURES - A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material and the core structure are configured to form a quantum-well channel in the shell material. | 09-17-2015 |
20150357432 | SYSTEMS AND METHODS FOR FABRICATING VERTICAL-GATE-ALL-AROUND DEVICES - Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region. | 12-10-2015 |
20150364358 | METHOD OF FORMING ISOLATION LAYER - According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure. | 12-17-2015 |
20160064493 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 03-03-2016 |