Patent application number | Description | Published |
20130157462 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 06-20-2013 |
20130196481 | METHOD OF PATTERNING FOR A SEMICONDUCTOR DEVICE - A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature. | 08-01-2013 |
20130280909 | METAL CUT PROCESS FLOW - A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features. | 10-24-2013 |
20140127897 | DUAL DAMASCENE PROCESS - A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects. | 05-08-2014 |
20140148005 | SEMICONDUCTOR DEVICE WITH SELF ALIGNED END-TO-END CONDUCTIVE LINE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques. | 05-29-2014 |
20140193974 | MULTI-PATTERNING METHOD AND DEVICE FORMED BY THE METHOD - A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns. | 07-10-2014 |
20140193980 | PATTERNED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. Accordingly, first patterned second hard mask (HM) region is patterned, thus forming the line end space structure associated with an end-to-end space. | 07-10-2014 |
20140193981 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 07-10-2014 |
20140273433 | DOUBLE PATTERNING METHOD - Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible. | 09-18-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20140377962 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 12-25-2014 |
20150047891 | Integrated Circuit Features with Fine Line Space and Methods for Forming the Same - A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material. | 02-19-2015 |
20150179450 | MULTI-PATTERNING METHOD AND DEVICE FORMED BY THE METHOD - A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns. | 06-25-2015 |
20150187591 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 07-02-2015 |
20150200095 | CUT FIRST SELF-ALIGNED LITHO-ETCH PATTERNING - The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a substrate having a multi-layer hard mask with a first layer and an underlying second layer. A first plurality of openings, cut according to the first cut layer, are formed to expose the second layer at a first plurality of positions corresponding to a first plurality of shapes of a SALE design layer. A spacer material is deposited onto sidewalls of the multi-layer hard mask to form a second cut layer. A second plurality of openings, cut according to the second cut layer, are formed to expose the second layer at a second plurality of positions corresponding to a second plurality of shapes of the SALE design layer. The second layer is etched according to the first and second plurality of openings. | 07-16-2015 |
20150200096 | CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING - The present disclosure relates to a method of performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a spacer material over a substrate having a multi-layer hard mask with a first layer and an underlying second layer to provide a first cut layer, and forming a reverse material over the spacer material to form a second cut layer. A second plurality of openings, cut according to the second cut layer, are formed to expose the second layer at a positions corresponding to a second plurality of shapes of a SALE design layer. A first plurality of openings, cut according to the first cut layer, are formed to expose the second layer at a positions corresponding to a first plurality of shapes of the SALE design layer. The second layer is etched according to the first and second plurality of openings. | 07-16-2015 |
20150206804 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A high-k/metal gate (HK/MG) and a conductive feature are disposed over a substrate, separated by a first dielectric layer. A global hard mask (GHM) layer is formed over the HK/MG, the conductive feature and the first dielectric layer. A second dielectric layer is then formed over the GHM layer. The second dielectric layer is etched to form a first opening to expose a portion of the HK/MG and a second opening to expose a portion of the conductive feature, by using the GHM layer as an etch stop layer. The GHM layer in the first opening and the second opening is then removed. | 07-23-2015 |
20150235897 | Reverse Tone Self-Aligned Contact - Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact. | 08-20-2015 |
20150255275 | High Performance Self Aligned Contacts and Method of Forming Same - A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region. | 09-10-2015 |
20150255283 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 09-10-2015 |
20150348796 | Nano Wire Structure and Method for Fabricating the Same - A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern. | 12-03-2015 |
20150348848 | SELF-ALIGNED NANOWIRE FORMATION USING DOUBLE PATTERNING - A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate. | 12-03-2015 |
20150364371 | SELF-ALIGNED INTERCONNECT WITH PROTECTION LAYER - An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug. | 12-17-2015 |
20150364380 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) and the corresponding device are disclosed. A high-k/metal gate (HK/MG) and a conductive feature are disposed over a substrate, separated by a first dielectric layer. A global hard mask (GHM) layer is formed over the HK/MG, the conductive feature and the first dielectric layer. A second dielectric layer is then formed over the GHM layer. The second dielectric layer is etched to form a first opening to expose a portion of the HK/MG and a second opening to expose a portion of the conductive feature, by using the GHM layer as an etch stop layer. The GHM layer in the first opening and the second opening is then removed. | 12-17-2015 |
20160005614 | Spacer Etching Process for Integrated Circuit Design - A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. | 01-07-2016 |
20160064248 | DOUBLE PATTERNING METHOD - In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines. | 03-03-2016 |
20160086887 | Method of Fine Line Space Resolution Lithography for Integrated Circuit Features Using Double Patterning Technology - A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material. | 03-24-2016 |