| Patent application number | Description | Published |
|---|
| 20090289273 | LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously. | 11-26-2009 |
| 20090289345 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes. | 11-26-2009 |
| 20100181589 | CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes. | 07-22-2010 |
| 20100289092 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 11-18-2010 |
| 20110079892 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad. | 04-07-2011 |
| 20110127666 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes. | 06-02-2011 |
| 20110169139 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole. | 07-14-2011 |
| 20130193520 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 08-01-2013 |
| 20130196470 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad. | 08-01-2013 |
| 20140113412 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes. | 04-24-2014 |
| Patent application number | Description | Published |
|---|
| 20110058095 | METHOD FOR USING FLASH TO ASSIST IN FOCAL LENGTH DETECTION - A method for assisting in focal length detection is applicable to a digital camera having the flash. The method includes the following steps. First, the flash of the digital camera is actuated and a first image is captured. Afterwards, a characteristic exposure value of the first image is calculated. A focus range comparison table is looked up according to the characteristic exposure value to obtain an initial focus position. Then, a focus procedure is performed according to the initial focus position to obtain a target focal length. | 03-10-2011 |
| 20110058096 | FAST FOCUSING METHOD FOR DIGITAL CAMERA - A fast focusing method for a digital camera is applied in an auto focusing stage for judging whether the digital camera needs to be refocused. The fast focusing method includes recording a system time after a previous focusing (defined as a first time); capturing a system time before a current focusing (defined as a second time); performing a fuzziness detection procedure to acquire a focus value when a difference obtained by subtracting the first time from the second time is greater than a focusing time threshold; setting a focusing focal length range covering a reference focal length when the focus value is between a lower limit focusing threshold and an upper limit focusing threshold; capturing images at different focusing focal lengths respectively in the focusing focal length range; calculating a contrast value of each image; calculating a target focal length from the contrast values through a quadratic curve approximation method. | 03-10-2011 |
| 20110063494 | CONTINUOUS FOCUSING METHOD FOR DIGITAL CAMERA - A continuous focusing method for a digital camera is described, which is applicable to determine whether the digital camera performs a focusing procedure or not when the digital camera switches from a first scene to a second scene in a live view stage. The continuous focusing method includes the following steps. A preview image of a second scene is obtained. A blur detection procedure is performed on the preview image, so as to acquire a corresponding focus value. It is determined whether the focus value exceeds a focusing threshold value or not; if not, a focusing procedure is performed; otherwise, if the focus value is greater than the focusing threshold value, the digital camera still maintains a current focusing focal length, which represents that a focusing focal length of the second scene is the same as that of the first scene. | 03-17-2011 |
| 20110069190 | FAST FOCUSING METHOD FOR DIGITAL CAMERA - A fast focusing method for a digital camera is applied in the digital camera to judge whether a focusing focal length of the digital camera needs to be adjusted in an auto focusing stage. The fast focusing method includes capturing a target image at a reference focal length; performing a blur detection procedure on the target image to acquire a focus value; setting a focusing focal length range covering the reference focal length when the focus value is between a lower limit focusing threshold and an upper limit focusing threshold; capturing corresponding comparison images at different focusing focal lengths respectively in the focusing focal length range; calculating a contrast value of each comparison image; and calculating the contrast values and a target focal length through a quadratic curve approximation method, and adjusting lenses of the digital camera to the set target focal length to perform shooting. | 03-24-2011 |
| 20120008038 | ASSISTING FOCUSING METHOD FOR FACE BLOCK - An assisting focusing method is applicable in an image capture device having an auto focusing (AF) procedure. The AF procedure has a preset sampling interval. The assisting focusing method includes the following steps. An image for focusing is captured. A face parameter of a face block in the image for focusing is calculated. According to the face parameter, a parameter-to-focus conversion table is looked up to acquire a focusing section. According to the focusing section and a face sampling interval, the AF procedure is performed to acquire a target focus. The face sampling interval is smaller than the preset sampling interval. | 01-12-2012 |
| 20120019709 | ASSISTING FOCUSING METHOD USING MULTIPLE FACE BLOCKS - A method using multiple face blocks for assisting focusing is applicable in an image capture device. The assisting focusing method includes the following steps. A focusing image is captured individually at a focusing distance. The focusing image has a plurality of face blocks. The face blocks in the focusing image are detected. Clarities of the face blocks in the focusing image are calculated with the image capture device. A face focal length corresponding to the face block is calculated according to the clarity corresponding to the face block. A target focal length is obtained according to the face focal length. | 01-26-2012 |
| Patent application number | Description | Published |
|---|
| 20090032945 | SOLDER BUMP ON A SEMICONDUCTOR SUBSTRATE - A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer. | 02-05-2009 |
| 20090283877 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL. | 11-19-2009 |
| 20110140248 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL. | 06-16-2011 |
| Patent application number | Description | Published |
|---|
| 20120091496 | SUBMOUNT AND MANUFACTURING METHOD THEREOF - A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency. | 04-19-2012 |
| 20120228745 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate. | 09-13-2012 |
| 20140045302 | Manufacturing Method of Submount - A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency. | 02-13-2014 |
| Patent application number | Description | Published |
|---|
| 20130229796 | LIGHT EMITTING DIODE BAR AND LIGHT EMITTING DIODE MODULE USING THE SAME - A light emitting diode (LED) bar and an LED module using the same are provided. The LED bar includes a long shaped substrate, a plurality of first LEDs and a second LED. Two long parallel edges of the long shaped substrate are extended along a first direction. The long shaped substrate includes a non-connecting area and a connecting area located at an end of the long shaped substrate. The first LEDs are interlaced and disposed in the non-connecting area and between the two long sides. Each first LED has a first long axis disposed along the first direction. The second LED has a second long axis disposed in the connecting area and along a second direction. The first direction and the second direction are intersected at a predetermined angle. | 09-05-2013 |
| 20140063820 | LAMP TUBE - A lamp tube includes a light transmission tube, a heat dissipation structure, a die bonding substrate and at least one light source. The light transmission tube includes first guiding rails disposed on opposite positions of the inner wall thereof. The first guising rails and the inner wall of the light transmission tube form first grooves. The heat dissipation structure inserts into the light transmission tube, and includes a die bonding area, extending arms downwardly extended from opposite sides of the heat dissipation structure, and connecting arms connected to the extending arms. Each of the extending arms includes second guiding rails and second grooves. The second guiding rail is engaged with the first groove, and the first guiding rail is engaged with the second groove. The die bonding substrate is placed on the die bonding area. The light source is placed on the die bonding substrate. | 03-06-2014 |
| 20140078771 | LIGHT DEVICE - A light device includes a light transmission tube, a heat sink, a light bar, and two end caps. The light transmission tube has two securing parts. Each of the securing parts includes a first rib and a second rib, and a guide-track groove is formed between the first and second ribs. The heat sink includes a first plate body and a second plate body. The first plate body is curved and abutted on an inner wall of the light transmission tube, and the second plate body is curved toward the first plate body. Two terminals of the first plate body are connected to two terminals of the second plate body to form two connecting parts for coupling with the guide-track grooves. The light bar is disposed on the second plate body. The end caps are respectively connected to two terminals of the light transmission tube. | 03-20-2014 |
