Patent application number | Description | Published |
20080237798 | MEMORY CELL AND PROCESS FOR MANUFACTURING THE SAME - A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively. | 10-02-2008 |
20080259679 | Programming method of magnetic random access memory - A programming method of a magnetic random access memory (MRAM) is provided. The magnetic random access memory includes a first magnetic pinned layer, a second magnetic pinned layer and a magnetic free layer. The first magnetic pinned layer is pinned at a first magnetic direction. The second magnetic pinned layer is pinned at a second magnetic direction. The magnetic free layer is magnetized into the first magnetic direction or the second magnetic direction. The programming method includes the following the steps. In the step (a), an additional magnetic field is applied onto the magnetic free layer. In the step (b), a first electron current is emitted through the magnetic free layer to magnetize the magnetic free layer into the first magnetic direction or the second magnetic direction. | 10-23-2008 |
20080278995 | Magnetic memory and memory cell thereof and method of manufacturing the memory cell - A magnetic memory, a memory cell thereof, and a method of manufacturing the memory cell are provided. The memory cell of the magnetic memory includes a bottom contact layer, a bit line, a magnetic stack structure and a dielectric material. The bit line is disposed over the bottom contact layer. The magnetic stack structure is disposed between the bottom contact layer and the bit line. The dielectric material at least fills between the bottom contact layer and the bit line and surrounds the magnetic stack structure. A gap is formed between the dielectric material and the magnetic stack structure. During programming of the memory cell, the magnetic stack structure generates heat, and the gap delays heat loss. | 11-13-2008 |
20090072211 | Resistive random access memory and method for manufacturing the same - A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell. | 03-19-2009 |
20090166604 | RESISTANCE TYPE MEMORY DEVICE - A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity. | 07-02-2009 |
20100112810 | Resistive random access memory and method for manufacturing the same - A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell. | 05-06-2010 |
20110250729 | METHOD FOR FABRICATING MEMORY - A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer. | 10-13-2011 |
20120154076 | ATTENUATOR - An attenuator is provided. The attenuator includes a first resistor, which is electrically connected to an input node; a nanowire, which is connected to the first resistor in series, for filtering low frequency signal; a second resistor, having an output node, which is electrically connected to the nanowire; wherein when a low frequency voltage is received by the input node, the nanowire filters the low frequency voltage such that the output node generates an output voltage lower than the low frequency voltage. | 06-21-2012 |
20120244062 | METHOD FOR PREPARING NITRIDE NANOMATERIALS - The present invention relates to a method for preparing nitride nanomaterials, including: providing a first precursor and a second precursor, in which the first precursor is a transition metal precursor, a group IIIA precursor, a group IVA precursor or a mixture thereof, and a second precursor is a nitrogen-containing aromatic compound; and heating the first precursor with the second precursor to form a nitride nanomaterial. Accordingly, the present invention provides a simpler, nontoxic, more widely applied and low-cost method for preparing nitride nanomaterials. | 09-27-2012 |
20140077150 | SEMICONDUCTOR MEMORY STORAGE ARRAY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer. | 03-20-2014 |
Patent application number | Description | Published |
20130161755 | THIN FILM TRANSISTOR AND FABRICATING METHOD - A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed. | 06-27-2013 |
20140099756 | THIN FILM TRANSISTOR AND FABRICATING METHOD - A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed. | 04-10-2014 |