Patent application number | Description | Published |
20130034966 | CHEMICAL DISPERSION METHOD AND DEVICE - A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided. | 02-07-2013 |
20130075831 | METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER - A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer. | 03-28-2013 |
20130082304 | FinFET Device and Method Of Manufacturing Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure. | 04-04-2013 |
20130092984 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins. | 04-18-2013 |
20130093026 | SELECTIVE FIN-SHAPING PROCESS USING PLASMA DOPING AND ETCHING FOR 3-DIMENSIONAL TRANSISTOR APPLICATIONS - A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin. | 04-18-2013 |
20130113072 | 3D Capacitor and Method of Manufacturing Same - A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different. | 05-09-2013 |
20130249010 | METAL GATE SEMICONDUCTOR DEVICE - Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer. | 09-26-2013 |
20130270647 | STRUCTURE AND METHOD FOR NFET WITH HIGH K METAL GATE - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal. | 10-17-2013 |
20140203333 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal. | 07-24-2014 |
20140203351 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together. | 07-24-2014 |
20140206156 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure. | 07-24-2014 |
20140206166 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins. | 07-24-2014 |
20140209984 | Semiconductor Device With Multi Level Interconnects And Method Of Forming The Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure. | 07-31-2014 |
20140319626 | Metal Gate Stack Having TiAlCN as Work Function Layer and/or Blocking/Wetting Layer - A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer. | 10-30-2014 |
20140339631 | Innovative Approach of 4F2 Driver Formation for High-Density RRAM and MRAM - Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array. | 11-20-2014 |
20140367800 | SEMICONDUCTOR DEVICE WITH STRAIN TECHNIQUE - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a fin structure disposed over the substrate in the gate region. The fin structure includes a first semiconductor material layer as a lower portion of the fin structure, a semiconductor oxide layer as a middle portion of the fin structure and a second semiconductor material layer as an upper portion of the fin structure. The semiconductor device also includes a dielectric feature disposed between two adjacent fin structures over the substrate. A top surface of the dielectric feature located, in a horizontal level, higher than the semiconductor oxide layer with a distance d. The semiconductor device also includes a high-k (HK)/metal gate (MG) stack disposed in the gate region, including wrapping over a portion of the fin structure. | 12-18-2014 |
20150035020 | Systems and Methods for Fabricating Semiconductor Devices at Different Levels - Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures. | 02-05-2015 |
20150054039 | FinFet Device with Channel Epitaxial Region - The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse. | 02-26-2015 |
20150132911 | SELECTIVE FIN-SHAPING PROCESS - A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins. | 05-14-2015 |
20150194426 | SYSTEMS AND METHODS FOR FABRICATING FINFETS WITH DIFFERENT THRESHOLD VOLTAGES - Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure. | 07-09-2015 |
20150236114 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function. | 08-20-2015 |
20150279846 | ANTIFUSE ARRAY AND METHOD OF FORMING ANTIFUSE USING ANODIC OXIDATION - A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material. | 10-01-2015 |
Patent application number | Description | Published |
20130056826 | Multi-Fin Device and Method of Making Same - A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned. | 03-07-2013 |
20130113073 | Integrated Circuit having a MOM Capacitor and Method of Making Same - An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor. | 05-09-2013 |
20130273705 | Multi-Fin Device and Method of Making Same - A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned. | 10-17-2013 |
20140117454 | FinFET with Dummy Gate on Non-Recessed Shallow Trench Isolation (STI) - An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region. | 05-01-2014 |
20140197458 | FinFET Device and Method of Fabricating Same - An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions. | 07-17-2014 |
20140239354 | FinFETs and Methods for Forming the Same - A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric. | 08-28-2014 |
20140239396 | Metal Gate and Gate Contact Structure for FinFET - An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact. | 08-28-2014 |
20140239404 | FInFET Structure and Method for Forming the Same - A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process. | 08-28-2014 |
20140252442 | Method and Structure for Vertical Tunneling Field Effect Transistor and Planar Devices - The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET. | 09-11-2014 |
20140252469 | FinFETs with Strained Well Regions - A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. | 09-11-2014 |
20140252496 | Gate Contact Structure for FinFET - An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width. | 09-11-2014 |
20140264289 | Structure and Method for Vertical Tunneling Field Effect Transistor with Leveled Source and Drain - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa. | 09-18-2014 |
20140319462 | BUFFER LAYER OMEGA GATE - A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions. | 10-30-2014 |
20140361336 | Fin Structure of Semiconductor Device - The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width. | 12-11-2014 |
20150035017 | Contact Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle. | 02-05-2015 |
20150054040 | FINFETS WITH STRAINED WELL REGIONS - A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band. | 02-26-2015 |
20150069474 | Isolation Structure of Fin Field Effect Transistor - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration. | 03-12-2015 |
20150091099 | FinFETs with Gradient Germanium-Containing Channels - A method includes forming a semiconductor fin, forming a dummy gate on a top surface and sidewalls of the semiconductor fin, and removing the dummy gate to form a recess. The semiconductor fin is exposed to the recess. After the dummy gate is removed, an oxidation is performed on the semiconductor fin to form a condensed germanium-containing fin in the recess, and a silicon oxide layer on a top surface and sidewalls of the condensed germanium-containing fin. The method further includes forming a gate dielectric over the condensed germanium-containing fin, and forming a gate electrode over the gate dielectric. | 04-02-2015 |
20150102386 | Passivated and Faceted for Fin Field Effect Transistor - A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed. | 04-16-2015 |
20150108544 | Fin Spacer Protected Source and Drain Regions in FinFETs - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region. A fin spacer is on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions. | 04-23-2015 |
20150144998 | Fin Structure of Semiconductor Device - A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized. | 05-28-2015 |
20150179756 | Metal Gate and Gate Contact Structure for FinFET - An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact. | 06-25-2015 |
20150236016 | Contact Structure of Semiconductor Device - A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate. | 08-20-2015 |
20150243751 | Contact Etch Stop Layers of a Field Effect Transistor - The disclosure relates to a field effect transistor. An exemplary structure for a field effect transistor comprises a substrate; a source region and a drain region disposed in the substrate; a gate structure over the substrate comprising sidewalls and a top surface, wherein the gate structure interposes the source region and the drain region; a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; an interlayer dielectric layer over the CESL; a gate contact extending through the interlayer dielectric layer; and a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm. | 08-27-2015 |
20150263159 | FINFET Structure and Method for Fabricating the Same - A device comprises a substrate comprising silicon, a fin structure comprising a lower portion formed of silicon and enclosed by an isolation region, a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer, an upper portion formed of silicon, wherein the upper portion comprises a channel and a silicon-carbon layer formed between the middle portion and the upper portion, a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region and a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region. | 09-17-2015 |
20150311111 | Fin Structure of Semiconductor Device - The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width. | 10-29-2015 |