| Patent application number | Description | Published |
|---|
| 20100126531 | METHOD AND APPARATUS FOR CLEANING SEMICONDUCTOR DEVICE FABRICATION EQUIPMENT USING SUPERCRITICAL FLUIDS - A process of cleaning a semiconductor device fabrication equipment is provided. In one embodiment, the semiconductor device fabrication equipment is placed in a chamber; a fluid is introduced into the chamber; a pressure and temperature of the fluid is controlled to bring the fluid to a supercritical state; the semiconductor device fabrication equipment is cleaned by having the supercritical fluid contact the semiconductor device fabrication equipment; the supercritical fluid is removed from the chamber; and the semiconductor device fabrication equipment is removed from the chamber. | 05-27-2010 |
| 20100140716 | N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer. | 06-10-2010 |
| 20100163078 | SPINNER AND METHOD OF CLEANING SUBSTRATE USING THE SPINNER - A method includes spinning a semiconductor wafer about an axis normal to a major surface of the wafer. The wafer is translated in a direction parallel to the major surface with an oscillatory motion, while spinning the wafer. A material is sprayed from first and second nozzles or orifices at respective first and second locations on the major surface of the wafer simultaneously while spinning the wafer and translating the wafer. | 07-01-2010 |
| 20100167506 | INDUCTIVE PLASMA DOPING - In some embodiments, a method of doping a semiconductor wafer disposed on a pedestal electrode in an inductive plasma chamber includes generating a plasma having a first voltage with respect to ground in the inductive plasma chamber, and applying a radio frequency (RF) voltage with respect to ground to the pedestal electrode in the inductive plasma chamber. The positive RF voltage is based on the first voltage of the plasma. | 07-01-2010 |
| 20100178772 | METHOD OF FABRICATING HIGH-K METAL GATE DEVICES - The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [Fâ] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than â1.4 volts. | 07-15-2010 |
| 20100190274 | RTP SPIKE ANNEALING FOR SEMICONDUCTOR SUBSTRATE DOPANT ACTIVATION - A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength. | 07-29-2010 |
| 20110086504 | METHODS FOR FORMING INTEGRATED CIRCUITS - A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed. | 04-14-2011 |
| 20110156166 | High Temperature Anneal for Aluminum Surface Protection - The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench. | 06-30-2011 |
| 20110195570 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios. | 08-11-2011 |
| 20110250725 | METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK - A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure. | 10-13-2011 |
| 20120064715 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up. | 03-15-2012 |
| 20120094448 | METHOD OF FABRICATING EPITAXIAL STRUCTURES - A method for fabricating an integrated device is disclosed. The disclosed method provides improved formation selectivity of epitaxial films over a pre-determined region designed for forming an epi film and a protective layer preferred not to form an epi, polycrystalline, or amorphous film thereon during an epi film formation process. In an embodiment, the improved formation selectivity is achieved by providing a nitrogen-rich protective layer to decrease the amount of growth epi, polycrystalline, or amorphous film thereon. | 04-19-2012 |
| 20120202156 | CLEANING PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION - A method of making an integrated circuit is provided. The method includes providing a substrate having a photosensitive layer. The photosensitive layer is exposed to a radiation beam. The exposed photosensitive layer is developed in a first chamber. In the first chamber, a cleaning process is performed on the developed photosensitive layer. The cleaning process includes using a rinse solution including at least one of ozone, hydrogen peroxide, and oxalic acid. | 08-09-2012 |
| 20130023094 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid. | 01-24-2013 |
| 20130034966 | CHEMICAL DISPERSION METHOD AND DEVICE - A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided. | 02-07-2013 |
| 20130045606 | SEMICONDUCTOR DEVICE CLEANING METHOD AND APPARATUS - A method includes providing a wafer and providing a first spray bar spaced a distance from the wafer. A first spray is dispensed from the first spray bar onto a first portion (e.g., half) of the wafer. Thereafter, the wafer is rotated. A second spray is dispensed from the first spray bar onto a second portion (e.g., half) of the rotated wafer. In embodiments, a plurality of spray bars are positioned above the wafer. One or more of the spray bars may be tunable in separation distance and/or angle of dispensing. | 02-21-2013 |
| 20130068248 | SEMICONDUCTOR DEVICE CLEANING METHOD - The present disclosure provides a method including providing a chamber having a first inlet and a second inlet. A solution of a de-ionized (DI) water and an acid (e.g., a dilute acid) is provided to the chamber via the first inlet. A carrier gas (e.g., N | 03-21-2013 |
| 20130074872 | IN-SITU BACKSIDE CLEANING OF SEMICONDUCTOR SUBSTRATE - The present disclosure provides a method and apparatus for cleaning a semiconductor wafer. In an embodiment of the method, a single wafer cleaning apparatus is provided and a wafer is positioned in the apparatus. A first chemical spray is dispensed onto a front surface of the wafer. A back surface of the wafer is cleaned while dispensing the first chemical spray. The cleaning of the back surface may include a brush and spray of cleaning fluids. An apparatus operable to clean the front surface and the back surface of a single semiconductor wafer is also described. | 03-28-2013 |
| 20130110276 | MULTI-FACTOR ADVANCED PROCESS CONTROL METHOD AND SYSTEM FOR INTEGRATED CIRCUIT FABRICATION | 05-02-2013 |
| 20130171746 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-04-2013 |
| 20130174982 | METAL HARD MASK FABRICATION - The present disclosure provides for methods of fabricating a metal hard mask and a metal hard mask fabricated by such methods. A method includes flowing at least one metal reactant gas into a reaction chamber configured to perform chemical vapor deposition (CVD), wherein the at least one metal reactant gas includes a metal-halogen gas or a metal-organic gas. The method further includes depositing a hard mask metal layer by CVD using the at least one metal reactant gas. | 07-11-2013 |
| 20130270617 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer. | 10-17-2013 |
