Patent application number | Description | Published |
20130067197 | COMPUTER SUBSYSTEM AND COMPUTER SYSTEM - The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system. | 03-14-2013 |
20130290634 | Data Processing Method and Apparatus - Embodiments of the present invention disclose a data processing method and apparatus. The method includes: first receiving an operation command, then searching, according to a memory address, a Cache memory in a Cache controller for data to be operated, and storing the operation command in a missed command buffer area in the Cache controller when the data to be operated is not found through searching in the Cache memory; then, storing data sent by an external memory in a data buffer area of the Cache controller after sending a read command to the external memory, and finally processing, according to a missed command, the data acquired from the external memory and the data carried in the missed command. The present invention applies to the field of computer systems. | 10-31-2013 |
20140013182 | DATA PROCESSING METHOD, APPARATUS AND SYSTEM - A method according to an embodiment of the present disclosure comprising: receiving a read instruction transmitted by a host device, the read instruction including a first address; reading first data together with a first CRC code and a first ECC which are associated with the first data from a memory based on the first address; and performing error detection on the first data based on the first CRC code, and performing error correction on the first data based on the first ECC if an error is detected. With the embodiments of the disclosure, the CRC code with better capability of error detection is adopted to perform error detection on the data. If any error is detected, error correction is performed using the ECC. Thus, it is possible to overcome the problem as to insufficient capability of error detection of the ECC in the prior art, thereby improving the system performance. | 01-09-2014 |
20140032731 | Recursive, All-to-All Network Topologies - An apparatus comprises an interconnection network comprising N | 01-30-2014 |
20140032853 | Method for Peer to Peer Cache Forwarding - A home node for selecting a source node using a cache coherency protocol, comprising a logic unit cluster coupled to a directory, wherein the logic unit cluster is configured to receive a request for data from a requesting cache node, determine a plurality of nodes that hold a copy of the requested data using the directory, select one of the nodes using one or more selection parameters as the source node, and transmit a message to the source node to determine whether the source node stores a copy of the requested data, wherein the source node forwards the requested data to the requesting cache node when the requested data is found within the source node, and wherein some of the nodes are marked as a Shared state corresponding to the cache coherency protocol. | 01-30-2014 |
20140032854 | Coherence Management Using a Coherent Domain Table - A computer program product comprising computer executable instructions stored on a non-transitory medium that when executed by a processor cause the processor to perform the following: assign a first, second, third, and fourth coherence domain address to a cache data, wherein the first and second address provides the boundary for a first coherence domain, and wherein the third and fourth address provides the boundary for a second coherence domain, inform a first resource about the first coherence domain prior to the first resource executing a first task, and inform a second resource about the second coherence domain prior to the second resource executing a second task. | 01-30-2014 |
20140033209 | Handling of Barrier Commands for Computing Systems - A computing system for handling barrier commands includes a memory, an interface, and a processor. The memory is configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command. The interface is coupled to the memory and is configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier spreading range and receive a barrier completion notification messages from the target computing system. The pre-barrier computing probe is configured to instruct the target computing system to monitor a status of a transaction that needs to be executed for the barrier command to be completed. The processor is coupled to the interface and is configured to determine a status of the barrier command based on the received barrier completion notification messages. | 01-30-2014 |
20140036680 | Method to Allocate Packet Buffers in a Packet Transferring System - A method comprising receiving a credit status from a second node comprising a plurality of credits used to manage the plurality of allocations of storage space in a buffer of the second node, wherein each of the plurality of allocations are dedicated to a different packet type, instructing the second node to use the credit dedicated to a second priority packet type for storing a first priority packet type, wherein the first priority is higher than the second priority, and wherein the credit status reflects the credits for the first priority packet type having reached a minimum value, and transmitting the first priority packet to the second node. | 02-06-2014 |
20140036919 | Forward Progress Assurance and Quality of Service Enhancement in a Packet Transferring System - A method comprising detecting at least one Quality of Service (QoS) requirement is met that indicates a very important packet (VIP) is outstanding from a source node in a multi-hop network comprising multiple nodes, sending an initiation message to an adjacent node in response to the detection that may activate a protocol in which a reserved channel is activated, and receiving the VIP via the reserved channel. Also, a method comprising receiving an initiation message from an adjacent node in a multi-hop network that comprises information identifying the VIP comprising a source node, a destination node, a packet type, wherein the initiation message activates a protocol in which a reserved channel is activated, searching for the VIP identified by the initiation message, and forwarding the VIP promptly if present via the reserved channel or forwarding an initiation message to adjacent nodes closer to the source node. | 02-06-2014 |
20140036929 | Phase-Based Packet Prioritization - A network node comprises a receiver configured to receive a first packet, a processor coupled to the receiver and configured to process the first packet, and prioritize the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and a transmitter coupled to the processor and configured to transmit the first packet. An apparatus comprises a processor coupled to the memory and configured to generate instructions for a packet prioritization scheme, wherein the scheme assigns priority to packet transactions based on closeness to completion, and a memory coupled to the processor and configured to store the instructions. A method comprises receiving a first packet, processing the first packet, prioritizing the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and transmitting the first packet. | 02-06-2014 |
20140036930 | Priority Driven Channel Allocation for Packet Transferring - A method comprising advertising to a second node a total allocation of storage space of a buffer, wherein the total allocation is less than the capacity of the buffer, wherein the total allocation is partitioned into a plurality of allocations, wherein each of the plurality of allocations is advertised as being dedicated to a different packet type, and wherein a credit status for each packet type is used to manage the plurality of allocations, receiving a packet of a first packet type from the second node, and storing the packet to the buffer, wherein the space in the buffer occupied by the first packet type exceeds the advertised space for the first packet type due to the packet. | 02-06-2014 |
20140040561 | HANDLING CACHE WRITE-BACK AND CACHE EVICTION FOR CACHE COHERENCE - A method implemented by a computer system comprising a first memory agent and a second memory agent coupled to the first memory agent, wherein the second memory agent has access to a cache comprising a cache line, the method comprising changing a state of the cache line by the second memory agent, and sending a non-snoop message from the second memory agent to the first memory agent via a communication channel assigned to snoop responses, wherein the non-snoop message informs the first memory agent of the state change of the cache line. | 02-06-2014 |
20140052905 | Cache Coherent Handshake Protocol for In-Order and Out-of-Order Networks - Disclosed herein is a processing network element (NE) comprising at least one receiver configured to receive a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes, and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver. | 02-20-2014 |
20140052916 | Reduced Scalable Cache Directory - A processing network comprising a cache configured to store copies of memory data as a plurality of cache lines, a cache controller configured to receive data requests from a plurality of cache agents, and designate at least one of the cache agents as an owner of a first of the cache lines, and a directory configured to store cache ownership designations of the first cache line, and wherein the directory is encoded to support substantially simultaneous ownership of the first cache line by a plurality but less than all of the cache agents. Also disclosed is a method comprising receiving coherent transactions from a plurality of cache agents, and storing ownership designations of a plurality of cache lines by the cache agents in a directory, wherein the directory is configured to support storage of substantially simultaneous ownership designations for a plurality but less than all of the cache agents. | 02-20-2014 |
20140164724 | METHOD AND APPARATUS FOR PROCESSING SYSTEM COMMAND DURING MEMORY BACKUP - A method and an apparatus for processing a system command during memory backup. The method includes: acquiring a write address corresponding to a write operation command; if data corresponding to the write address has been read from a raw memory area but is not written to a backup memory area, mapping the write operation command to the raw memory area, and writing data to the write address in the raw memory area according to the write operation command; and deducting a set value from the write address to obtain an initial address to subsequently read data from the raw memory area. According to the embodiments of the present invention, a problem of system command blocking is solved during a memory backup operation, so that a system command is processed in a timely manner. | 06-12-2014 |