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| 20080287071 | EXPANDABLE WIRELESS TRANSCEIVER - An expandable wireless transceiver is provided. The expandable wireless transceiver includes an antenna, a receiver, a transmitter and a switch connector. The antenna detects an electromagnetic signal in surrounding space and receives a signal with a first central frequency according to the detection result. The receiver receives the signal based on the detection result of the antenna. The transmitter outputs a radio-frequency signal. A third connection terminal of the switch connector provides a connective path to an expansion antenna. According to the coupling condition of the third connection terminal, the switch connector delivers the radio-frequency signal to its second connection terminal or third connection terminal. Thus, the radio-frequency signal with a second central frequency is transmitted to surrounding space through the antenna or the expansion antenna, wherein the second central frequency and the first central frequency are both in a specific band. | 11-20-2008 |
| 20120154173 | Wireless Signal Transceiver and Blind Spot Detection System - A wireless signal transceiver for a blind spot detection system includes a first substrate, a radio-frequency processing unit formed on the first substrate for transmitting a wireless signal and receiving a reflecting signal of the transmitted wireless signal, and a complex programmable logic device controlled by a digital signal processor for controlling operations of the radio-frequency processing unit according to at least a control command of the digital signal processor, so as to detect whether an object exists within a specific range. | 06-21-2012 |
| 20130027266 | Unsymmetrical Dipole Antenna - An unsymmetrical dipole antenna includes a grounding element, a radiating element, and a feed-in wire. The grounding element includes a first short side metal plane and a first long side metal plane. The radiating element includes a second short side metal plane and a second long side metal plane. The feed-in wire includes a metal wire, coupled to the second short side metal plane for transmitting a feed-in signal; an insulation layer, covering the metal wire; a metal weave, covering the insulation layer, having one terminal coupled to the first short side metal plane of the grounding element, and another terminal coupled to a system ground of the wireless communication device; and a protective layer, covering the metal weave. A size of the grounding element and a size of the radiating element are irrelative. | 01-31-2013 |
| 20130154890 | ANTENNA DEVICE - An antenna device is provided and includes a bottom, two monopole antennas, and a cover assembled with the bottom. A projection plane is defined perpendicular to the bottom. The two monopole antennas substantially symmetrically protrude from the bottom, and a gap is formed between the two monopole antennas. Projections of the two monopole antennas on the projection plane intersect with each other. Each of the two monopole antennas includes a first frequency receiving portion adjacent to the bottom, a second frequency receiving portion, and a connection portion located between the first frequency receiving portion and the second frequency receiving portion. A slot is formed through the connection portion to adjust a received frequency of the first or second frequency receiving portion. An accommodating space is formed between the cover and the bottom to accommodate the two monopole antennas. | 06-20-2013 |
| 20130335286 | Decoupling Circuit and Antenna Device - A decoupling circuit for enhancing isolation of two monopole antennas is disclosed. The two monopole antennas substantially symmetrically stand on a bottom, and a gap is formed between the two monopole antennas. The decoupling circuit includes a grounding element located on the bottom and electrically connected to a ground, a connection bar substantially perpendicular to the bottom, including a first terminal electrically connected to the grounding element, a second terminal extending to the gap, a first branch extending from the second terminal of the connection bar to a first monopole antenna of the two monopole antennas, and a second branch extending from the second terminal of the connection bar to a second monopole antenna of the two monopole antennas. | 12-19-2013 |
| 20140118130 | AUTOMOBILE WARNING METHOD AND AUTOMOBILE WARNING SYSTEM UTILIZING THE SAME - An automobile warning method and an automobile warning system are provided. The automobile warning method is disclosed, implemented by an automobile warning system on a vehicle, wherein the automobile warning system includes a microwave reflective detection device and a control device, including: emitting, by the microwave reflective detection device, a microwave signal for detecting whether a mobile object is present in a blind spot of the vehicle; and when the presence of the mobile object is detected, changing, by the control device, a state of a controlled device of the vehicle. | 05-01-2014 |
| 20140125543 | Decoupling Circuit and Antenna Device - A decoupling circuit for enhancing isolation of two antennas is disclosed. The two antennas are substantially symmetrically disposed on a substrate. The decoupling circuit includes a first and second metal strips parallel disposed between the two antennas and electrically connected to a ground, a connection strip electrically connected between terminals of the first and second metal strips, to substantially form a doorframe structure, a first comb structure comprising a plurality of metal segments parallel to each other, disposed on the substrate, electrically connected to and perpendicular to the first metal strip, and a second comb structure comprising a plurality of metal segments parallel to each other, disposed on the substrate, electrically connected to and perpendicular to the second metal strip. | 05-08-2014 |
| 20140145909 | Antenna and Array Antenna - An antenna includes a radiating element with a shape substantially conforming to a quadrilateral, a grounding and feed-in element, substantially surrounding the radiating element and having an opening formed near to a fourth side of the radiating element, wherein the grounding and feed-in element is electrically connected to a ground at one side of the opening and is electrically connected to a signal feed-in terminal at another side of the opening, a first connection element, having a terminal electrically connected to a first side and the fourth side of the radiating element, and another terminal electrically connected to the grounding and feed-in element, and a second connection element, having a terminal electrically connected to a third side and the fourth side of the radiating element, and another terminal electrically connected to the grounding and feed-in element. | 05-29-2014 |
| 20140159885 | Blind Spot Detection System - A blind spot detection system comprises an alarm, capable of generating an alarm signal; a plurality of sensors, each for emitting a radio signal and receiving a reflecting signal of the emitted radio signal, to detect whether an object exists within a specific range and generate a detection result accordingly; and a control module, for receiving at least one vehicle information from the OBD system and controlling the alarm to generate the alarm signal according to the at least one vehicle information and a plurality of detection results generated by the plurality of sensors. | 06-12-2014 |
| 20140168004 | Radar System and Control Method thereof - A radar system comprises a transmitting device comprising a reference frequency source, for generating a reference frequency signal; a direct-digital synthesizer, coupled to the reference frequency source, for generating a synthesized frequency signal according to the reference frequency signal; a phase lock loop, coupled to the direct-digital synthesizer, for converting the synthesized frequency signal to an output signal; a transmitting antenna, coupled to the phase lock loop, for emitting the output signal to the air; and a loop switch module, coupled to the phase lock loop, for switching the phase lock loop between an open loop mode and a closed loop mode; and at least one receiving device, for receiving at least one wireless signal, and processing the at least one wireless signal according to the output signal generated by the phase lock loop. | 06-19-2014 |
| 20140203960 | Power Divider and Radio-frequency Transceiver System - A radio-frequency transceiver system comprises a radio-frequency processing unit, a transmitting microwave network and a receiving microwave network, wherein the transmitting microwave network comprises a transmitting power divider for distributing main power of transmitting signals to two central sub-array antennas of four sub-array antennas, and the receiving microwave network comprises a receiving power divider for providing power mainly from a first input terminal and a second input terminal for a receiving route, and providing power mainly from the second input terminal and a third input terminal for another receiving route. | 07-24-2014 |
| 20140313069 | Compound Circuit Board and Radar Device - A compound circuit board for a radar device includes a first substrate including a plurality of trace layers having a first trace layer formed with a digital signal processing unit and an electronic control unit in a first area, a second substrate including a plurality of trace layers having a second trace layer formed with an antenna module in a second area, and a prepreg layer between the first and second substrates for connecting the first and second substrates, wherein the first area and the second area in a first projecting result generated by projecting the first trace layer on the second trace layer are substantially overlapped. | 10-23-2014 |
| 20150276929 | Signal Processing Method and Device for Frequency-Modulated Continuous Waveform Radar System - A signal processing method for a frequency-modulated continuous waveform (FMCW) radar system includes receiving a plurality of feedback signals from a plurality of targets and performing analog to digital conversion on the plurality of feedback signals to obtain a digital receiving signal corresponding to the plurality of feedback signals, performing a window function on the digital receiving signal to obtain a window transformation signal corresponding to the digital receiving signal, performing time-domain to frequency-domain conversion on the window transformation signal to obtain a spectrum signal of the window transformation signal, performing two beat frequency detections on the spectrum signal, and determining distances and speeds of the plurality of targets in comparison to the FMCW radar system according to results of the two beat frequency detections. | 10-01-2015 |
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| 20140062580 | Diode Formed of PMOSFET and Schottky Diodes - A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET. | 03-06-2014 |
| 20140253190 | Multiple Power Domain Electronic Device and Related Method - An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit. | 09-11-2014 |
| 20150070057 | Multiple Power Domain Electronic Device and Related Method - An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit. | 03-12-2015 |
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| 20090051413 | APPARATUS AND METHOD FOR INCREASING CHARGE PUMP EFFICIENCY - A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage. | 02-26-2009 |
| 20120106259 | Adaptive Control of Programming Currents for Memory Cells - A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation. | 05-03-2012 |
| 20130093499 | POWER SWITCH AND OPERATION METHOD THEREOF - A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level. | 04-18-2013 |
| 20130307080 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 11-21-2013 |
| 20150015223 | Low Dropout Regulator and Related Method - A device includes an error amplifier, a standby current source, a charging current source, a voltage divider, and a first switch. The error amplifier has a negative input terminal and a positive input terminal. The standby current source has a control terminal electrically connected to an output terminal of the error amplifier. The voltage divider has an input terminal electrically connected to an output terminal of the standby current source, and an output terminal electrically connected to the positive input terminal of the error amplifier. The charging current source has a control terminal electrically connected to the output terminal of the error amplifier. The first switch has a first terminal electrically connected to an input terminal of the charging current source, and a second terminal electrically connected to a first power supply node. | 01-15-2015 |
| 20150117131 | MEMORY DEVICES - A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed. | 04-30-2015 |
| 20150131372 | MEMORY CONTROLLER, MEMORY DEVICE AND METHOD OF OPERATING - A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell. | 05-14-2015 |
| 20150221383 | MULTIPLE-TIME PROGRAMMABLE MEMORY - A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage. | 08-06-2015 |
| 20150269974 | SOURCE LINE VOLTAGE REGULATION SCHEME FOR LEAKAGE REDUCTION - An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and an array of memory cells connected to the one or more source lines. The generator unit is configured to set a first voltage signal of each pull-up unit of the one or more pull-up units. Each pull-up unit of the one or more pull-up units is connected with the corresponding source line of the one or more source lines and is configured to set a current of the corresponding source line of the one or more source lines. The array of memory cells is electrically connected to the one or more source lines and one or more bit lines. | 09-24-2015 |
| 20160035398 | MEMORY DEVICES - A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed | 02-04-2016 |
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| 20110179682 | FLOWING SAND PICTURE - A flowing sand picture flowing sand picture includes a transparent, flat box-like picture frame holding therein a fluid, multiple heavy granular materials and multiple lightweight granular materials. Each heavy granular material has a specific gravity higher than the fluid and each lightweight granular material has a specific gravity lower than the fluid. When the transparent, flat box-like picture frame is turned upside down, the granular materials float up and down through one another, showing a picture of dynamic variation. | 07-28-2011 |
| 20120036747 | FLOWING SAND PICTURE - A flowing sand picture flowing sand picture includes a transparent, flat box-like picture frame holding therein a fluid, multiple heavy granular materials and multiple lightweight granular materials. Each heavy granular material has a specific gravity higher than the fluid and each lightweight granular material has a specific gravity lower than the fluid. When the transparent, flat box-like picture frame is turned upside down, the granular materials float up and down through one another, showing a picture of dynamic variation. | 02-16-2012 |
| 20120117835 | SAND-FLOWING PICTURE DEVICE - A sand-flowing picture device includes a transparent, flat and sealed container, a fluid, first sand particulates with a specific gravity higher than the fluid and second sand particulates with a specific gravity lower than the fluid. The second sand particulates with a predetermined quantity fewer than the first sand particulates so as to provide slots which the first sand particulates can pass through gradually downwardly when the first sand particulates fall on and along a layer formed by the second sand particulates that rise upon inversion of the container in a vertical position. The container is substantially bubble-free. Therefore, the device can show a sand picture of dynamic variation and form a new and different decorative pattern. | 05-17-2012 |
| 20130097902 | FLOWING SAND PICTURE - A flowing sand picture flowing sand picture includes a transparent, flat box-like picture frame holding therein a fluid, multiple heavy granular materials and multiple lightweight granular materials. Each heavy granular material has a specific gravity higher than the fluid and each lightweight granular material has a specific gravity lower than the fluid. When the transparent, flat box-like picture frame is turned upside down, the granular materials float up and down through one another, showing a picture of dynamic variation. | 04-25-2013 |
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| 20130187807 | ANTENNA APPARATUS AND ANTENNA SWITCH CIRCUIT - An antenna device and an antenna switch circuit are provided. The antenna device comprises a first antenna, an antenna detection circuit, a switch control circuit, and a controller. The first antenna is configured to transmit an RF signal. The antenna detection circuit comprises an inductor configured to detect a second antenna. The switch control circuit is coupled to the antenna detection circuit and configured to generate a first control signal indicative of the presence of the second antenna upon the detection thereof. The controller is coupled to the first antenna, the antenna detection circuit and the switch control circuit, and configured to receive the first control signal and connect to the second antenna when the first control signal indicates the presence of the second antenna. | 07-25-2013 |
| 20140023125 | Signal Transceiver and Adaptive Impedance Switch Circuit - A signal transceiver includes a connector for receiving a signal, a band-pass filter coupled to the connector for filtering the signal, a front-end module for demodulating the signal and an adaptive impedance switch circuit coupled between the band-pass filter and the front-end module for switching an impedance value between the band-pass filter and the front-end module. | 01-23-2014 |
| 20140314131 | Signal Transceiver with Enhanced Return Loss in Power-off State - A signal transceiver with enhanced return loss in a power-off state includes a connector, a band-pass filter, a front-end module and an impedance transformation circuit. The impedance transformation circuit is coupled between the band-pass filter and the front-end module for transforming an input impedance of the signal transceiver, and includes an input terminal coupled to the band-pass filter for receiving a signal; an output terminal coupled to the front-end module for outputting the signal to the front-end module; an impedance transforming unit; and a power source input circuit coupled to the impedance transforming unit for providing a power source; wherein the impedance transforming unit is coupled between the power source input circuit and the input terminal, for transforming the input impedance of the signal transceiver. | 10-23-2014 |
| 20160079693 | CONNECTOR AND PRINTED CIRCUIT BOARD MODULE HAVING THE SAME - A connector including a conductive casing, a terminal, a first insulation structure and a conductive structure is provided. The conductive casing has an inner wall. The terminal includes a first section and a second section. The first section is disposed in the conductive casing, and the first section and the inner wall have a gap therebetween. The second section is located outside the conductive casing. The first insulation structure is disposed between the first section and the inner wall. The conductive structure is electrically connected to the conductive casing and has an inclined plane. The inclined plane is aligned to the second section, the second section and the inclined plane have a gap therebetween, and the inclined plane is parallel to a extending direction of the second section. In addition, a printed circuit board module having the connector is also provided. | 03-17-2016 |
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| 20140084479 | Integrated Circuit Formed Using Spacer-Like Copper Deposition - A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer. | 03-27-2014 |
| 20140124932 | INTEGRATED CIRCUIT DEVICE HAVING A COPPER INTERCONNECT - A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench. | 05-08-2014 |
| 20140138838 | Method of Semiconducotr integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench. | 05-22-2014 |
| 20140187044 | ADDITION OF CARBOXYL GROUPS PLASMA DURING ETCHING FOR INTERCONNECT RELIABILITY ENHANCEMENT - The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO | 07-03-2014 |
| 20140252633 | METHOD OF FABRICATING AN AIR GAP USING A DAMASCENE PROCESS AND STRUCTURE OF SAME - The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps. | 09-11-2014 |
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| 20140349481 | Air-Gap Formation in Interconnect Structures - A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps. | 11-27-2014 |
| 20150093899 | Semiconductor Device Manufacturing Methods - Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method. | 04-02-2015 |
| 20150132952 | Air Gap Formation by Damascene Process - The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps. | 05-14-2015 |
| 20150155171 | Lithography Using High Selectivity Spacers for Pitch Reduction - A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. | 06-04-2015 |
| 20150155198 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask. | 06-04-2015 |
| 20150162205 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask. | 06-11-2015 |
| 20150187696 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature. | 07-02-2015 |
| 20150255389 | Integrated Circuit Interconnects and Methods of Making Same - A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween. | 09-10-2015 |
| 20150340233 | Semiconductor Device Manufacturing Methods - Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method. | 11-26-2015 |
| 20150340240 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask. | 11-26-2015 |
| 20150380300 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask. | 12-31-2015 |
| 20160035571 | Lithography Using High Selectivity Spacers for Pitch Reduction - A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. | 02-04-2016 |
| 20160099174 | METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE - Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element. | 04-07-2016 |
