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| 20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 12-02-2010 |
| 20130145078 | METHOD FOR CONTROLLING MEMORY ARRAY OF FLASH MEMORY, AND FLASH MEMORY USING THE SAME - A control method for a Flash memory array and a Flash memory is disclosed. The Flash memory array includes a plurality of blocks which are classified into groups and each group includes at least one block. The control method includes the steps of: recognizing an attribute of data transferred from a host, obtaining a storage group selected from the groups based on the attribute of the data, and storing the data into the blocks of the storage group and thereby the blocks of a same group store data of a same attribute; and performing a valid data collection, restricted to the blocks belonging to a same group, to release blocks of space. | 06-06-2013 |
| 20130311698 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller determines a minimum erase count from the erase counts of the spare blocks and the data blocks, adds a first difference to the minimum erase count to obtain a jail threshold, compares the erase counts of the spare blocks with the jail threshold to obtain a plurality of jail blocks with the erase counts greater than the jail threshold, and confines the jail blocks to a jail pool. | 11-21-2013 |
| 20130311701 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current data block, and determines whether the current data block is full. When the current data block is full, the controller updates at least one table according to the information of the current data block. | 11-21-2013 |
| 20130311702 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - A data storage device is coupled to a host and includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein a spare block count indicates a total number of the spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the spare block count is less than a spare block count threshold when the current programming page is the first page, and sets data move information for a data merge process when the spare block count is less than the spare block count threshold. | 11-21-2013 |
| 20130311703 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - A data storage includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein the spare blocks with erase counts higher than a hot threshold are determined as hot spare blocks, and a hot spare block count indicates a total number of the hot spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the hot spare block count is greater than zero when the current programming page is the first page, and sets data move information for a wear-leveling process when the hot spare block count is greater than zero. | 11-21-2013 |
| 20130311704 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current programming data block, determines whether a current programming page is a first page of the current programming data block, determines whether data move information is set when the current page is not the first page, and when the data move information is set, perform a data move process according to the data move information within a limited time period. | 11-21-2013 |
| 20130311705 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a plurality of flash memory areas and a controller. Each of the flash memory areas comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, selects a target memory area to which the target data is to be written from the flash memory areas, sets a physical address range parameter according to the target memory area, sets a spare block pool parameter according to the target memory area, and writes the target data to a current data block of the target memory area. | 11-21-2013 |
| 20130326120 | DATA STORAGE DEVICE AND OPERATING METHOD FOR FLASH MEMORY - A data storage device and operating method for a FLASH memory are disclosed. The data storage device includes a FLASH memory and a controller. The FLASH memory includes a first block and a second block. The first and second blocks each includes a plurality of pages. The controller executes a firmware to determine whether a data segment from a host is a complete page segment. When the data segment is a complete page segment, the controller stores the data segment into the first block. When the data segment is an incomplete page segment, the controller stores the data into segment the second block. | 12-05-2013 |
| 20130326121 | DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table. | 12-05-2013 |
| 20130339575 | DATA STORAGE DEVICE AND DATA TRIMMING METHOD - A data storage device is disclosed. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each block comprises a plurality of pages, and each page comprises a plurality of data trimming units which is a smallest unit for data modification. After a data trimming process has been performed on an address range of the flash memory, the controller determines a last page corresponding to an ending address of the address range, determines whether data values stored in the last page with addresses subsequent to the ending address are all equal to a specific data pattern, and sets the value of a trimming flag corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending address are all equal to the specific data pattern. | 12-19-2013 |
| 20140068158 | FLASH STORAGE DEVICE AND CONTROL METHOD FOR FLASH MEMORY - A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged. | 03-06-2014 |
| 20140078825 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - Storage space allocation and a wear leveling technique for a FLASH memory module are disclosed. The FLASH memory module includes a plurality of FLASH chips. A controller for the FLASH memory module divides the storage space of the FLASH memory module into Xblocks for management of the FLASH memory module. The controller erases at least one Xblock for space release and moves data on Xblocks for wear leveling. | 03-20-2014 |
| 20140082265 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - A mapping table H2F update technique for a FLASH memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the FLASH memory in accordance with a group count of a buffer block of the FLASH memory. The group count reflects a logical address distribution of write data buffered in the buffer block and with non-updated logical-to-physical address mapping information. The higher the group count, the more dispersed the logical address distribution. In this manner, each update of the logical-to-physical address mapping table just takes a short time. | 03-20-2014 |
| 20140250258 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method. The control method includes the following steps: dividing a plurality of blocks of the FLASH memory into groups to be accessed via different channels; allocating at least one set of cache spaces in a random access memory for temporary write data storage for the different channels; separating write data issued from a host to correspond to the plurality of channels; and, when data arrangement for every channel has been completed in one set of cache spaces, writing the data that has been arranged in the set of cache spaces to the FLASH memory via the plurality of channels corresponding to the different cache spaces of the set of cache spaces. | 09-04-2014 |
| 20140379964 | DATA STORAGE DEVICE AND DATA FETCHING METHOD FOR FLASH MEMORY - A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block. | 12-25-2014 |
| 20150067233 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - A mapping table H | 03-05-2015 |
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| 20080308829 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 12-18-2008 |
| 20100258834 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 10-14-2010 |
| 20110101400 | LIGHT EMITTING DIODES (LEDS) WITH IMPROVED LIGHT EXTRACTION BY ROUGHENING - Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device. | 05-05-2011 |
| 20110316039 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 12-29-2011 |
| 20120074384 | PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES - Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non-(or low) thermally conductive and/or non-(or low) electrically conductive carrier substrate that has been removed. | 03-29-2012 |
| 20120146083 | VERTICAL LED WITH CURRENT-GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided. | 06-14-2012 |
| 20120168714 | VERTICAL LIGHT EMITTING DIODE (VLED) DIE AND METHOD OF FABRICATION - A vertical light emitting diode (VLED) die includes a first metal having a first surface and an opposing second surface; a second metal on the second surface of the first metal; a p-type semiconductor layer on the first surface of the first metal; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. | 07-05-2012 |
| 20120168716 | Light Emitting Diode (LED) Die Having Stepped Substrates And Method Of Fabrication - A light emitting diode (LED) die includes a first substrate having a first surface and an opposing second surface; a second substrate on the second surface of the first substrate; a p-type semiconductor layer on the first surface of the first substrate; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. | 07-05-2012 |
| 20130334982 | METHOD FOR GUIDING CURRENT IN A LIGHT EMITTING DIODE (LED) DEVICE - Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided. | 12-19-2013 |
| 20140051197 | METHOD FOR FABRICATING A VERTICAL LIGHT EMITTING DIODE (VLED) DIE HAVING EPITAXIAL STRUCTURE WITH PROTECTIVE LAYER - A method for fabricating a vertical light emitting diode (VLED) die includes the steps of: providing a substrate; forming an epitaxial structure on the substrate; forming an electrically insulative insulation layer covering the lateral surfaces of the epitaxial structure; forming an electrically non-conductive material on the electrically insulative insulation layer; and forming a mirror on the p-doped layer, with the electrically insulative insulation layer configured to protect the epitaxial structure during formation of the mirror. | 02-20-2014 |
| 20140151630 | PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES - Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non-(or low) thermally conductive and/or non-(or low) electrically conductive carrier substrate that has been removed. | 06-05-2014 |
| 20140151635 | METHOD FOR FABRICATING A LIGHT EMITTING DIODE (LED) DIE HAVING PROTECTIVE SUBSTRATE - A method for fabricating a light emitting diode die includes the steps of providing a carrier substrate and forming an epitaxial structure on the carrier substrate including a first type semiconductor layer, a multiple quantum well (MQW) layer on the first type semiconductor layer configured to emit light, and a second type semiconductor layer on the multiple quantum well (MQW) layer. The method also includes the steps of forming a plurality of trenches through the epitaxial structure, forming a reflector layer on the second type semiconductor layer, forming a seed layer on the reflector layer and in the trenches, and forming a substrate on the seed layer having an area configured to protect the epitaxial structure. | 06-05-2014 |
| 20140339496 | Vertical Light Emitting Diode (VLED) Dice Having Confinement Layers With Roughened Surfaces And Methods Of Fabrication - A vertical light emitting diode (VLED) die includes an epitaxial structure having a first-type confinement layer, an active layer on the first-type confinement layer configured as a multiple quantum well (MQW) configured to emit light, and a second-type confinement layer having a roughened surface. In a first embodiment, the roughened surface includes a pattern of holes with a depth (d) in a major surface thereof surrounded by a pattern of protuberances with a height (h) on the major surface. In a second embodiment, the roughened surface includes a pattern of primary protuberances surrounded by a pattern of secondary protuberances. | 11-20-2014 |
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| 20090159322 | THROUGH HOLE CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission. | 06-25-2009 |
| 20090161298 | HYBRID CAPACITOR - A hybrid capacitor is provided which includes a substrate, at least one plate capacitor and at least one through hole capacitor. The substrate has through holes and the plate capacitors are on the substrate. At least one through hole capacitor and at least one plate capacitor are in parallel. The through hole capacitor at least includes an anode layer, a first dielectric layer, a first cathode layer and a second cathode layer. The anode layer is disposed on an inner surface of at least one through hole, and a surface of the anode layer is a porous structure. The first dielectric layer is disposed on the porous structure of the anode layer and covered with the first cathode layer. The first cathode layer is covered with the second cathode layer. A conductivity of the second cathode layer is larger than a conductivity of the first cathode layer. | 06-25-2009 |
| 20110157775 | DECOUPLING DEVICE - A decoupling device includes a lead frame, a capacitor unit, a metal layer, and a high dielectric organic-inorganic composite material layer. The lead frame includes a cathode terminal portion and an anode terminal portion. The capacitor unit is disposed on the lead frame. The capacitor unit includes a cathode portion, an anode portion, and an insulation portion located between the cathode portion and the anode portion. The cathode portion is electrically connected to the cathode terminal portion, and the anode portion is electrically connected to the anode terminal portion. The high dielectric organic-inorganic composite material layer is connected to the capacitor unit in parallel via the metal layer. | 06-30-2011 |
| 20120162852 | DECOUPLING DEVICE - A decoupling device including a lead frame and at least one capacitor unit assembly is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions located at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor unit assembly includes multiple capacitor elements. The multiple capacitor elements of the capacitor unit assembly is connected in parallel, arrayed on the same plane and disposed on the lead frame. Each capacitor element has a cathode portion and an anode portion opposite to each other. The cathode portion of the capacitor element is electrically connected with the cathode terminal portion. The anode portion of the capacitor element is electrically connected with the anode terminal portion. When multiple capacitor unit assemblies exists, the capacitor unit assemblies are arrayed in a stacked way. | 06-28-2012 |
| 20120171573 | HYBRID MATERIALS USING IONIC PARTICLES - A separator substrate include a substrate having a bulk portion and a surface portion, the surface portion having at least one porous area with a net charge; and ionic particles coupling to at least a part of the at least one porous area. The ionic particles have a net charge of an opposite sign to the net charge of the at least one porous area. The coupling between the part of the at least one porous area and the ionic particles may result in at least one of a good electrochemical performance, chemical stability, thermal stability, wettability, and mechanical strength of the separator substrate. | 07-05-2012 |
| 20120171576 | NON-AQUEOUS ELECTROLYTE AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME - A non-aqueous electrolyte including a lithium salt, an organic solvent, and an electrolyte additive is provided. The electrolyte additive is a meta-stable state nitrogen-containing polymer formed by reacting Compound (A) and Compound (B). Compound (A) is a monomer having a reactive terminal functional group. Compound (B) is a heterocyclic amino aromatic derivative as an initiator. A molar ratio of Compound (A) to Compound (B) is from 10:1 to 1:10. A lithium secondary battery containing the non-aqueous electrolyte is further provided. The non-aqueous electrolyte of this disclosure has a higher decomposition voltage than a conventional non-aqueous electrolyte, such that the safety of the battery during overcharge or at high temperature caused by short-circuit current is improved. | 07-05-2012 |
| 20120171579 | NON-AQUEOUS ELECTROLYTE AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME - A non-aqueous electrolyte including a lithium salt, an organic solvent, and an electrolyte additive is provided. The electrolyte additive is a meta-stable state nitrogen-containing polymer formed by reacting Compound (A) and Compound (B). Compound (A) is a monomer having a reactive terminal functional group. Compound (B) is a heterocyclic amino aromatic derivative as an initiator. A molar ratio of Compound (A) to Compound (B) is from 10:1 to 1:10. A lithium secondary battery containing the non-aqueous electrolyte is further provided. The non-aqueous electrolyte of this disclosure has a higher decomposition voltage than a conventional non-aqueous electrolyte, such that the safety of the battery during overcharge or at high temperature caused by short-circuit current is improved. | 07-05-2012 |
| 20120172558 | META-STABLE STATE NITROGEN-CONTAINING POLYMER - A meta-stable state nitrogen-containing polymer formed by reacting Compound (A) and Compound (B) is described. Compound (A) is a monomer having a reactive terminal functional group. Compound (B) is a heterocyclic amino aromatic derivative as an initiator. The molar ratio of Compound (A) to Compound (B) is from 10:1 to 1:10. The meta-stable state nitrogen-containing polymer has a variance less than 2% in its narrow molecular weight distribution after being retained at 55° C. for one month. | 07-05-2012 |
| 20120172593 | META-STABLE STATE NITROGEN-CONTAINING POLYMER - A meta-stable state nitrogen-containing polymer formed by reacting Compound (A) and Compound (B) is described. Compound (A) is a monomer having a reactive terminal functional group. Compound (B) is a heterocyclic amino aromatic derivative as an initiator. The molar ratio of Compound (A) to Compound (B) is from 10:1 to 1:10. The meta-stable state nitrogen-containing polymer has a variance less than 2% in its narrow molecular weight distribution after being retained at 55° C. for one month. | 07-05-2012 |
| 20130120903 | DECOUPLING DEVICE AND FABRICATING METHOD THEREOF - A decoupling device including a lead frame, multiple capacitor units, a protective layer and a packaging element is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions disposed at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor units are connected in parallel and disposed on the lead frame. Each capacitor unit has a cathode portion and an opposite anode portion. The cathode portion is electrically connected with the cathode terminal portion. The anode portion is electrically connected with the anode terminal portion. The protective layer wraps at least one of the anode portion and the cathode portion of the capacitor unit. The packaging element covers the lead frame, the capacitor units and the protective layer. The packaging element exposes a bottom surface of the lead frame. | 05-16-2013 |
| 20140233158 | DECOUPLING DEVICE - A decoupling device including a lead frame and at least one capacitor unit assembly is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions located at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor unit assembly includes multiple capacitor elements. The multiple capacitor elements of the capacitor unit assembly is connected in parallel, arrayed on the same plane and disposed on the lead frame. Each capacitor element has a cathode portion and an anode portion opposite to each other. The cathode portion of the capacitor element is electrically connected with the cathode terminal portion. The anode portion of the capacitor element is electrically connected with the anode terminal portion. When multiple capacitor unit assemblies exists, the capacitor unit assemblies are arrayed in a stacked way. | 08-21-2014 |
| 20140318612 | MANUFACTURING METHOD OF SILICON SOLAR CELL AND SILICON SOLAR CELL - A manufacturing method of a silicon solar cell and the silicon solar cell thereof are provided. A silicon substrate formed with a doped layer on a light receiving surface thereof is provided. First and second dielectric layers are respectively formed on the light receiving surface and the rear surface of the silicon substrate. A patterned second dielectric layer with an opening and a groove in the silicon substrate are formed by partially removing the second dielectric layer and the silicon substrate. First and second electrode compositions are respectively formed on the light receiving surface and the rear surface, and the second electrode composition is filled into the groove. After performing a high temperature process to co-firing the silicon substrate and the first and second electrode compositions, a first electrode and a second electrode are respectively formed on the light receiving surface and the rear surface. | 10-30-2014 |
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| 20110128354 | SYSTEM AND METHOD FOR OBTAINING CAMERA PARAMETERS FROM MULTIPLE IMAGES AND COMPUTER PROGRAM PRODUCTS THEREOF - Systems and methods for obtaining camera parameters from images are provided. First, a sequence of original images associated with a target object under circular motion is obtained. Then, a background image and a foreground image corresponding to the target object within each original image are segmented. Next, shadow detection is performed for the target object within each original image. A first threshold and a second threshold are respectively determined according to the corresponding background and foreground images. Each original image, the corresponding background image, the first and second threshold are used for obtaining silhouette data and feature information associated with the target object within each original image. At least one camera parameter is obtained based on the entire feature information and the geometry of circular motion. | 06-02-2011 |
| 20130058561 | PHOTOGRAPHIC SYSTEM - A photographic system for generating photos is provided. The photographic system comprises a photo composition unit, and a photo synthesizer. The photo composition unit is capable of determining an extracted view from a three dimensional (3D) scene. The photo synthesizer, coupled to the photo composition unit, is capable of synthesizing an output photo according to the extracted view. | 03-07-2013 |
| 20130163854 | IMAGE PROCESSING METHOD AND ASSOCIATED APPARATUS - An image processing method includes: receiving a plurality of images, the images being captured under different view points; and performing image alignment for the plurality of images by warping the plurality of images, where the plurality of images are warped according to a set of parameters, and the set of parameters are obtained by finding a solution constrained to predetermined ranges of physical camera parameters. In particular, the step of performing the image alignment further includes: automatically performing the image alignment to reproduce a three-dimensional (3D) visual effect, where the plurality of images is captured by utilizing a camera module, and the camera module is not calibrated with regard to the view points. For example, the 3D visual effect can be a multi-angle view (MAV) visual effect. In another example, the 3D visual effect can be a 3D panorama visual effect. An associated apparatus is also provided. | 06-27-2013 |
| 20130342735 | IMAGE PROCESSING METHOD AND IMAGE PROCESSING APPARATUS FOR PERFORMING DEFOCUS OPERATION ACCORDING TO IMAGE ALIGNMENT RELATED INFORMATION - An image processing method includes: receiving a plurality of input images; deriving an image alignment related information from performing an image alignment upon the input images; and generating a processed image by performing a defocus operation upon a selected image selected from the input images according to the image alignment related information. For example, the image processing method may be employed by an electronic device such as a mobile device. Thus, the mobile device may capture two or more images to generate the defocus visual effect, which is similar to professional long-focus lens. | 12-26-2013 |
| 20140075382 | IMAGE VIEWING METHOD FOR DISPLAYING PORTION OF SELECTED IMAGE BASED ON USER INTERACTION INPUT AND RELATED IMAGE VIEWING SYSTEM AND MACHINE READABLE MEDIUM - An image viewing method includes: determining at least a first partial image corresponding to a portion of a first image directly selected from a plurality of images, and driving a display apparatus according to the first partial image; in accordance with a user interaction input, determining a second partial image corresponding to a portion of a second image directly selected from the images; and driving the display apparatus according to at least the second partial image. In one implementation, the first image and the second image are spatially correlated, and a field of view (FOV) of each of the first image and the second image is larger than an FOV of the display apparatus. | 03-13-2014 |
| 20140160245 | METHOD AND APPARATUS FOR STEREOSCOPIC FOCUS CONTROL OF STEREO CAMERA - A stereoscopic control method includes: establishing a specific mapping relation between a specific disparity value and a specific set of a first focal setting value of a first sensor of a stereo camera and a second focal setting value of a second sensor of the stereo camera; and controlling stereoscopic focus of the stereo camera according to the specific mapping relation. Besides, a stereoscopic control apparatus includes a mapping unit and a focus control unit. The mapping unit is arranged for establishing at least a specific mapping relation between a specific disparity value and a specific set of a first focal setting value of a first sensor of a stereo camera and a second focal setting value of a second sensor of the stereo camera. The focus control unit is arranged for controlling stereoscopic focus of the stereo camera according to the specific mapping relation. | 06-12-2014 |
| 20140254917 | AUTO-CONVERGENCE SYSTEM WITH ACTIVE LEARNING AND RELATED METHOD AND MACHINE-READABLE MEDIUM THEREOF - An auto-convergence system includes a disparity unit, a convergence unit and an active learning unit. The disparity unit performs a disparity analysis upon an input stereo image pair, and accordingly obtains a disparity distribution of the input stereo image pair. The convergence unit adjusts the input stereo image pair adaptively according to the disparity distribution and a learned convergence range, and accordingly generates an output stereo image pair for playback. The active learning unit actively learns a convergence range during playback of stereo image pairs, and accordingly determines the learned convergence range. | 09-11-2014 |
| 20140285621 | VIDEO FRAME PROCESSING METHOD - A video frame processing method, which comprises: (a) capturing at least two video frames via a multi-view camera system comprising a plurality of cameras; (b) recording timestamps for each the video frame; (c) determining a major camera and a first sub camera out of the multi-view camera system, based on the timestamps, wherein the major camera captures a major video sequence comprising at least one major video frame, the first sub camera captures a video sequence of first view comprising at least one video frame of first view; (d) generating a first reference video frame of first view according to one first reference major video frame of the major video frames, which is at a reference timestamp corresponding to the first reference video frame of first view, and according to at least one the video frame of first view surrounding the reference timestamp; and (e) generating a multi-view video sequence comprising a first multi-view video frame, wherein the first multi-view video frame is generated based on the first reference video frame of first view and the first reference major video frame. | 09-25-2014 |
| 20140285635 | VIDEO FRAME PROCESSING METHOD - A video frame processing method, which comprises: (a) capturing at least one first video frame via a first camera; (b) capturing at least one second video frame via a second camera; and (c) adjusting one candidate second video frame of the second video frames based on one of the first video frame to generate a target single view video frame. | 09-25-2014 |
| 20140285637 | 3D IMAGE CAPTURE METHOD WITH 3D PREVIEW OF PREVIEW IMAGES GENERATED BY MONOCULAR CAMERA AND RELATED ELECTRONIC DEVICE THEREOF - A three-dimensional (3D) image capture method, employed in an electronic device with a monocular camera and a 3D display, includes at least the following steps: while the electronic device is moving, deriving a 3D preview image from a first preview image and a second preview image generated by the monocular camera, and providing 3D preview on the 3D display according to the 3D preview image, wherein at least one of the first preview image and the second preview image is generated while the electronic device is moving; and when a capture event is triggered, outputting the 3D preview image as a 3D captured image. | 09-25-2014 |
| 20140286567 | IMAGE PROCESSING METHOD AND ASSOCIATED APPARATUS - An image processing method includes: receiving a plurality of images, the images being captured under different view points; and performing image alignment for the plurality of images by warping the plurality of images, where the plurality of images are warped according to a set of parameters, and the set of parameters are obtained by finding a solution constrained to predetermined ranges of physical camera parameters. In particular, the step of performing the image alignment further includes: automatically performing the image alignment to reproduce a three-dimensional (3D) visual effect, where the plurality of images is captured by utilizing a camera module, and the camera module is not calibrated with regard to the view points. For example, the 3D visual effect can be a multi-angle view (MAV) visual effect. In another example, the 3D visual effect can be a 3D panorama visual effect. An associated apparatus is also provided. | 09-25-2014 |
| 20140340491 | APPARATUS AND METHOD FOR REFERRING TO MOTION STATUS OF IMAGE CAPTURE DEVICE TO GENERATE STEREO IMAGE PAIR TO AUTO-STEREOSCOPIC DISPLAY FOR STEREO PREVIEW - A stereo preview apparatus has an auto-stereoscopic display, an input interface, a motion detection circuit, and a visual transition circuit. The input interface receives at least an input stereo image pair including a left-view image and a right-view image generated from an image capture device. The motion detection circuit evaluates a motion status of the image capture device. The visual transition circuit generates an output stereo image pair based on the input stereo image pair, and outputs the output stereo image pair to the auto-stereoscopic display for stereo preview, wherein the visual transition circuit refers to the evaluated motion status to configure adjustment made to the input stereo image pair when generating the output stereo image pair. | 11-20-2014 |
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| 20100259233 | Direct Current Converter - A direct current converter includes a first node, a second node, an input voltage terminal, an output voltage terminal, a bootstrap source terminal, a low-voltage terminal, a control module for generating a control signal, a driving-stage circuit coupled to the input voltage terminal, the first node, the second node, the control module, and the low-voltage terminal, an output-stage circuit coupled to the second node and the output voltage terminal, and a bootstrap circuit including a capacitor coupled between the first node and the second node, a fault detector for outputting a switch signal, and a cascade unit coupled to the bootstrap source terminal, the first node, the control module, and the fault detector for controlling connection between the bootstrap source terminal and the first node according to the switch signal and the control signal. | 10-14-2010 |
| 20100259238 | Direct Current Converter - A direct current converter includes a first node, a second node, an input voltage terminal end, an output voltage terminal, a control power terminal, a low-voltage end, a control module for generating a control signal, a driving-stage circuit coupled to the input voltage terminal, the first node, the second node, the control module, and the low-voltage end, an output-stage circuit coupled to the second node and the output voltage terminal, and a bootstrap circuit including a capacitor coupled between the first node and the second node, and a cascade unit coupled to the control power terminal, the first node, and the control module for controlling connection between the control power terminal and the first node according to the control signal. | 10-14-2010 |
| 20110043178 | Electronic Device with Power Switch Capable of Regulating Power Dissipation - An electronic device with a power switch capable of regulating power dissipation includes a power supply device; a power switch, for providing an output voltage; and a current regulating circuit, which includes an adaptive control unit, for outputting a regulating signal, according to the voltage difference between the power supply device and the output voltage; and a switch control unit, for outputting a switch control signal to control the magnitude of the current through the power switch, according to the regulating signal. | 02-24-2011 |
| 20110317314 | Short Circuit Protection Circuit, Short Circuit Protection Method and Power Supply Device Thereof - A short circuit protection circuit for a power supply device includes a driving transistor, for controlling to output an input voltage to a load according to a first control voltage; a shutdown transistor, coupled with the driving transistor, for controlling a level of the first control voltage according to a second control voltage; and an energy storage module, coupled with the shutdown transistor, for storing energy of the input voltage, to output a specific voltage as the second control voltage in a specific interval after short-circuit occurs. | 12-29-2011 |
| 20140015503 | BOOT-STRAP CIRCUIT AND VOLTAGE CONVERTING DEVICE THEREOF - A boot-strap circuit for a voltage converting device includes a boot-strap capacitor; a charging module, for charging the boot-strap capacitor; and a protection module, for detecting a capacitor voltage of the boot-strap capacitor and adjusting conducting statuses of one of an upper-bridge switch and a lower-bridge switch of the voltage converting device according to the capacitor voltage and a duty cycle signal utilized for controlling conducting statuses of the upper-bridge switch and the lower-bridge switch. | 01-16-2014 |
| 20140062535 | Power-on Reset Circuit - A power-on reset circuit is disclosed. The power-on reset circuit includes a first resistor; a first transistor, including a first terminal coupled to a second terminal of the first resistor, and a control terminal for receiving a reference voltage; a second resistor, including a first terminal coupled to a second terminal of the first transistor; a second transistor, including a first terminal coupled to a second terminal of the first resistor, and a control terminal coupled to a second terminal of the second transistor and utilized for receiving an input voltage; and a comparator, including a first input terminal for receiving a comparison voltage, and a second input terminal for receiving the reference voltage, for generating a power-on reset signal according to the comparison voltage and the reference voltage. | 03-06-2014 |
| 20140145641 | Single Wire Signal Process Method and Circuit - A signal processing method for a single wire, includes receiving an input signal via the single wire, wherein the input signal includes a plurality of pulse signals; generating a plurality of bits corresponding to the plurality of pulse signals according to a plurality of widths of the plurality of pulse signals and forming a source code; and decoding the source code to generate a control code; wherein when a width of a first pulse signal of the plurality of pulse signals is smaller than a first duration, a first bit corresponding to the first pulse signal is a first bit value and when a width of a second pulse signal of the plurality of pulse signals is greater than a second duration, a second bit corresponding to the second pulse signal is a second bit value. | 05-29-2014 |
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| 20080258813 | Sense Amplifiers Operated Under Hamming Distance Methodology - A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs. | 10-23-2008 |
| 20090290446 | Memory Word-line Tracking Scheme - A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter. | 11-26-2009 |
| 20110158007 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 06-30-2011 |
| 20110188326 | DUAL RAIL STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control. | 08-04-2011 |
| 20110194362 | WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT - A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array. | 08-11-2011 |
| 20120020176 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain. | 01-26-2012 |
| 20120061764 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas. | 03-15-2012 |
| 20120092939 | SINGLE-ENDED SENSING SCHEME FOR MEMORY - A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground. | 04-19-2012 |
| 20120195139 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 08-02-2012 |
| 20120206953 | MEMORY EDGE CELL - A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively. | 08-16-2012 |
| 20130010560 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node. | 01-10-2013 |
| 20130094307 | BIT LINE VOLTAGE BIAS FOR LOW POWER MEMORY DESIGN - In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV. | 04-18-2013 |
| 20130128655 | METHOD AND APPARATUS FOR DUAL RAIL SRAM LEVEL SHIFTER WITH LATCHING - An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output. | 05-23-2013 |
| 20130194860 | Tracking for Write Operations of Memory Devices - Some aspects of the present disclosure relate to write tracking techniques for memory devices. In some embodiments, a memory device includes an array of SRAM cells, wherein each SRAM cell includes a pair of cross-coupled inverters having complimentary storage nodes, and a pair of access transistors that allow selective access to the complimentary storage nodes, respectively. To help ensure that wordline and bitline pulses are of sufficient length and intensity, one or more write tracking cells track a wordline tracking signal, which is representative of a wordline pulse applied to a wordline. In response to the wordline tracking signal, the write tracking cell internally generates a signal that models bitline loading, and provides an output tracking signal based on the wordline tracking and bitline loading signals. Bitline and/or wordline pulses can then be set based on the output tracking signal. | 08-01-2013 |
| 20130194877 | MEMORY AND METHOD OF OPERATING THE SAME - A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit. | 08-01-2013 |
| 20130208533 | MEMORY HAVING READ ASSIST DEVICE AND METHOD OF OPERATING THE SAME - A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage. | 08-15-2013 |
| 20130286708 | MEMORY EDGE CELL - A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell. | 10-31-2013 |
| 20130311964 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device. | 11-21-2013 |
| 20140035664 | VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage. | 02-06-2014 |
| 20140036608 | TRACKING SIGNALS IN MEMORY WRITE OR READ OPERATION - A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal. | 02-06-2014 |
| 20140084374 | CELL DESIGN - One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example. | 03-27-2014 |
| 20140211570 | Memory Read Techniques using Miller Capacitance Decoupling Circuit - Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed. | 07-31-2014 |
| 20140266436 | Sense Amplifier - The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed. | 09-18-2014 |
| 20140269128 | SENSE AMPLIFIER - A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled between the first data line and the first I/O node. The second pass gate is coupled between the second data line and the second I/O node. The first circuit is coupled with the first I/O node and the second data line. The second circuit is coupled with the second I/O node and the first data line. The first circuit is configured to be turned off when the second data line has a first logical value and to be at least lightly turned on when the second data line has a voltage level between the first logical value and a second logical value different from the first logical value. The second circuit is configured to be turned off when the first data line has the first logical value and to be at least lightly turned on when the first data line has a voltage level between the first logical value and the second logical value. | 09-18-2014 |
| 20150021701 | MEMORY CELL ARRAY - A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line. | 01-22-2015 |
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| 20110097617 | Battery Set with Heat Conducting Jelly - A battery set filled with heat conducting jelly is disclosed, which comprises a shell, for housing a cooling unit; and a plurality of battery cells, each battery cell being disposed inside the shell while having a heat conducting jelly, featuring with electric insulation and heat conduction abilities, to be filled surrounding the periphery thereof and contacting with the outer surface of each battery cell. | 04-28-2011 |
| 20110215667 | MAGNETIC TRANSMISSION ASSEMBLY - A magnetic transmission assembly is adapted to integration with a motor or generator. The magnetic transmission assembly includes a rotor, a stator, and a magnetically conductive element. The rotor and the stator are sleeved coaxially and respectively have R and ST | 09-08-2011 |
| 20110215668 | MAGNETIC TRANSMISSION ASSEMBLY - A magnetic transmission assembly is adapted to integration with a motor or generator. The magnetic transmission assembly includes a rotor, a stator, and a magnetically conductive element. The rotor and the stator are sleeved coaxially and respectively have R and ST | 09-08-2011 |
| 20120169157 | COOLING MODULE AND WATER-COOLED MOTOR SYSTEM USING THE SAME - A cooling module and a water-cooled motor system using the same are provided. The cooling module comprises a main body and a first flow passage assembly. The main body comprises a first lateral portion and a second lateral portion opposite the first lateral portion. The first flow passage assembly, disposed in the main body, comprises a first flow passage and a second flow passage. The first flow passage has a first end and a second end, wherein the first end is adjacent to the first lateral portion, and the second end is adjacent to the second lateral portion. The second flow passage has a third end and a fourth end, wherein the third end is connected to the second end of the first flow passage, and the fourth end is adjacent to the first lateral portion. | 07-05-2012 |
| 20130140920 | STATOR ASSEMBLY STRUCTURE FOR AXIAL FLUX ELECTRIC MACHINE - A stator assembly structure for an axial flux electric machine is designed. The back iron for each silicon steel disk stator is formed into a specific structure with tooth-like protrusions for allowing the same to be integrated with the disk-type stator seat, while the disk-type stator seat is made of a material suitable for casting or mold forming. A coil is mounted on the disk stator, and a stator assembly is achieved by integrating the stator, the coil and the stator seat. The stator and the disk-type stator seat of the stator assembly are manufactured by using a one-piece cast or one-piece mold forming method so as to enable the contact surfaces of the stator and the stator seat to engage with each other even more tightly, and consequently enable the heat generated from the coil to be transmitted rapidly from the disk stator to the disk-type stator seat. | 06-06-2013 |
| 20140183930 | DETACHABLE POWER MODULE - A disassembled and assembled power module includes: a wheel shaft; a power module; a central shaft, arranged in the power module and passing through the wheel shaft; and an engaging unit, capable of fastening the central shaft to the wheel shaft. In an embodiment when the detachable power module is applied in an electric driven wheelchair, it enables the weight of the wheelchair to be reduced by simply detach and remove the detachable power from the wheelchair so that the electric driven wheelchair without the heavy power module can be carry and transport easily, and also the moving range of the electric driven wheelchair can be increased as its power module can be easily detached and replaced with another fully charged power module so that the range anxiety of the disabled person using the same or the assistant can be relieved. | 07-03-2014 |
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| 20100221849 | METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS - A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD. | 09-02-2010 |
| 20130075623 | MULTI-ION BEAM IMPLANTATION APPARATUS AND METHOD - An multi-ion beam implantation apparatus and method are disclosed. An exemplary apparatus includes an ion beam source that emits at least two ion beams; an ion beam analyzer; and a multi-ion beam angle incidence control system. The ion beam analyzer and the multi-ion beam angle incidence control system are configured to direct the emitted at least two ion beams to a wafer. | 03-28-2013 |
| 20130075624 | Beam Monitoring Device, Method, And System - A beam monitoring device, method, and system is disclosed. An exemplary beam monitoring device includes a one dimensional (1D) profiler. The 1D profiler includes a Faraday having an insulation material and a conductive material. The beam monitoring device further includes a two dimensional (2D) profiler. The 2D profiler includes a plurality of Faraday having an insulation material and a conductive material. The beam monitoring device further includes a control arm. The control arm is operable to facilitate movement of the beam monitoring device in a longitudinal direction and to facilitate rotation of the beam monitoring device about an axis. | 03-28-2013 |
| 20130110276 | MULTI-FACTOR ADVANCED PROCESS CONTROL METHOD AND SYSTEM FOR INTEGRATED CIRCUIT FABRICATION | 05-02-2013 |
| 20130140987 | ION IMPLANTATION WITH CHARGE AND DIRECTION CONTROL - The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode. | 06-06-2013 |
| 20130171336 | WAFER PROCESSING METHOD AND SYSTEM USING MULTI-ZONE CHUCK - In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones. | 07-04-2013 |
| 20130295753 | ION BEAM DIMENSION CONTROL FOR ION IMPLANTATION PROCESS AND APPARATUS, AND ADVANCED PROCESS CONTROL - A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate. | 11-07-2013 |
| 20140202383 | WAFER PROCESSING SYSTEM USING MULTI-ZONE CHUCK - A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer. The process chamber is configured to perform a treatment on a front side of the wafer. The front side is opposite the back side. The process chamber includes therein a multi-zone chuck. The multi-zone chuck is configured to support the back side of the wafer. The multi-zone chuck has a plurality of zones with controllable clamping forces for securing the wafer to the multi-zone chuck. The controller is coupled to the metrology chamber and the multi-zone chuck. The controller is configured to control the clamping forces in the corresponding zones in accordance with measured values of the thickness of the first layer in the corresponding zones. | 07-24-2014 |
| 20140235071 | SUBSTRATE RAPID THERMAL HEATING SYSTEM AND METHODS - A method and apparatus for rapid thermal heat treatment of semiconductor and other substrates is provided. A number of heat lamps arranged in an array or other configuration produce light and heat radiation. The light and heat radiation is directed through a heat slot that forms a radiation beam of high intensity light and heat. The radiation beam is directed to a platen that includes multiple substrates. The apparatus and method include a controller that controls rotational and translational motion of the platen relative to the heat slot and also controls the power individually and collectively supplied to the heat lamps. A program is executed which maneuvers the platen such that all portions of all substrates receive the desired thermal treatment, i.e. attain a desired temperature for a desired time period. | 08-21-2014 |
| 20140273420 | ION IMPLANTATION - One or more techniques or systems for ion implantation are provided herein. A pressure control module is configured to maintain a substantially constant pressure within an ion implantation or process chamber. Pressure is maintained based on an attribute of an implant layer, pressure data, feedback, photo resist (PR) outgassing, a PR coating rate, a space charge effect associated with the implant layer, etc. By maintaining pressure within the process chamber, effects associated with PR outgassing are mitigated, thereby mitigating neutralization of ions. By maintaining charged ions, better control over implantation of the ions is achieved, thus allowing ions to be implanted at a desired depth. | 09-18-2014 |
| Patent application number | Description | Published |
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| 20110136662 | CATALYTIC SEEDING CONTROL METHOD - A catalytic seeding control method is disclosed. A catalytic metal film is deposited on a substrate with a nonwettable inclined surface. The catalytic metal film is then melted to form metal droplets. The metal droplets roll along the nonwettable inclined surface and aggregate to form a singular catalytic seed on the bottom of the nonwettable inclined surface. Then, the location of the singular catalytic seed is precisely controlled. Also, the size of the catalytic seed is controlled by adjusting the size of the inclined surface and the thickness of the catalytic metal layer to grow a one-dimensional structure with specific localization and single well-aligned manipulated size. The structure is utilized for the integrated microelectronic device fabrication. | 06-09-2011 |
| 20120032320 | FLEXIBLE MICRO-SYSTEM AND FABRICATION METHOD THEREOF - A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems. | 02-09-2012 |
| 20120162852 | DECOUPLING DEVICE - A decoupling device including a lead frame and at least one capacitor unit assembly is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions located at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor unit assembly includes multiple capacitor elements. The multiple capacitor elements of the capacitor unit assembly is connected in parallel, arrayed on the same plane and disposed on the lead frame. Each capacitor element has a cathode portion and an anode portion opposite to each other. The cathode portion of the capacitor element is electrically connected with the cathode terminal portion. The anode portion of the capacitor element is electrically connected with the anode terminal portion. When multiple capacitor unit assemblies exists, the capacitor unit assemblies are arrayed in a stacked way. | 06-28-2012 |
| 20120323539 | Method and Non-Transitory Computer Readable Medium Thereof for Thermal Analysis Modeling - A method and a non-transitory computer readable medium thereof for thermal analysis modeling are provided. The method includes establishing an electrothermal network π model on the basis of electronic modules of an electronic system to define a heat source, propagation paths and a common base of the electronic system. Observation points in the electronic system are defined, in which each observation point is located at an isothermal surface enclosing a volume surrounding a reference point, and where the reference point is the heat source or one observation point. A heat conduction temperature difference and a heat convection temperature difference are calculated according to a power density function, a thermal conductivity coefficient and a distance vector between the reference point and each observation point. A temperature distribution is established according to the heat conduction and the heat convection temperature difference and a defined temperature of the common base. | 12-20-2012 |
| 20130120903 | DECOUPLING DEVICE AND FABRICATING METHOD THEREOF - A decoupling device including a lead frame, multiple capacitor units, a protective layer and a packaging element is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions disposed at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor units are connected in parallel and disposed on the lead frame. Each capacitor unit has a cathode portion and an opposite anode portion. The cathode portion is electrically connected with the cathode terminal portion. The anode portion is electrically connected with the anode terminal portion. The protective layer wraps at least one of the anode portion and the cathode portion of the capacitor unit. The packaging element covers the lead frame, the capacitor units and the protective layer. The packaging element exposes a bottom surface of the lead frame. | 05-16-2013 |
| 20130234314 | FLEXIBLE MICRO-SYSTEM AND FABRICATION METHOD THEREOF - A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems. | 09-12-2013 |
| 20140071591 | DECOUPLING DEVICE WITH THREE-DIMENSIONAL LEAD FRAME AND FABRICATING METHOD THEREOF - A decoupling device including a lead frame and at least one capacitor unit set is provided. The lead frame includes a cathode terminal portion and at least two anode terminal portions disposed at two sides of the cathode terminal portion and opposite to each other. The anode terminal portions are electrically connected through a conductive line. One of the anode terminal portions extends along a first direction to form an extending portion, and the extending portion is bended along a second direction perpendicular to the first direction to form an anode side plate. Each capacitor unit set includes a plurality of capacitor units. The capacitor unit sets are connected in parallel on a same plane and disposed on the lead frame. Each capacitor unit has a cathode portion electrically connected to the cathode terminal portion and an anode portion electrically connected to the anode side plate along the first direction. | 03-13-2014 |
| 20140233158 | DECOUPLING DEVICE - A decoupling device including a lead frame and at least one capacitor unit assembly is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions located at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor unit assembly includes multiple capacitor elements. The multiple capacitor elements of the capacitor unit assembly is connected in parallel, arrayed on the same plane and disposed on the lead frame. Each capacitor element has a cathode portion and an anode portion opposite to each other. The cathode portion of the capacitor element is electrically connected with the cathode terminal portion. The anode portion of the capacitor element is electrically connected with the anode terminal portion. When multiple capacitor unit assemblies exists, the capacitor unit assemblies are arrayed in a stacked way. | 08-21-2014 |
