Patent application number | Description | Published |
20090043955 | Configurable high-speed memory interface subsystem - A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal. | 02-12-2009 |
20090091349 | High speed multiple memory interface I/O cell - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode. | 04-09-2009 |
20090091987 | Multiple memory standard physical layer macro function - A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers. | 04-09-2009 |
20090187873 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist. | 07-23-2009 |
20100157700 | APPARATUS AND SYSTEMS FOR VT INVARIANT DDR3 SDRAM WRITE LEVELING - Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period. | 06-24-2010 |
20110084725 | HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode. | 04-14-2011 |
20110258587 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist. | 10-20-2011 |
20120194248 | NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA STROBE - A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects. | 08-02-2012 |
20120195141 | GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING MEMORY CONTROLLER AND SOURCE SYNCHRONOUS MEMORY - A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock. | 08-02-2012 |
20120278783 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path. | 11-01-2012 |