Patent application number | Description | Published |
20140203350 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack. | 07-24-2014 |
20140203351 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together. | 07-24-2014 |
20140203352 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature. | 07-24-2014 |
20140203374 | N/P Boundary Effect Reduction for Metal Gate Transistors - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates. | 07-24-2014 |
20140208283 | DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION - Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure. | 07-24-2014 |
20140231902 | Vertical Tunneling Field-Effect Transistor Cell - A tunneling field-effect transistor (TFET) device is disclosed. The TFET device includes a source contact on the source region, a plurality of gate contacts at a planar portion of a gate stack and a plurality of drain contacts disposed on a drain region. The source contact of the TFET device aligns with other two adjacent source contacts of other two TFET devices such that each source contact locates in one of three angles of an equilateral triangle. | 08-21-2014 |
20140256102 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units. | 09-11-2014 |
20140256144 | SEMICONDUCTOR FIN FORMATION METHOD AND MASK SET - A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks. | 09-11-2014 |
20140317581 | REVISING LAYOUT DESIGN THROUGH OPC TO REDUCE CORNER ROUNDING EFFECT - The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design. | 10-23-2014 |
20150048456 | METAL GATE FEATURES OF SEMICONDUCTOR DIE - A semiconductor die comprises two or more active regions over a substrate. A first set of dummy blocks are over the substrate, in contact with one another, and completely surrounding at least one of the two or more active regions. A second set of dummy blocks are over the substrate and farther from the at least one active region surrounded by the first set of dummy blocks than the dummy blocks of the first set of dummy blocks. Each of the dummy blocks of the first set of dummy blocks has individual surface areas, each of the dummy blocks of the second set of dummy blocks has individual surface areas, and the individual surface areas of each of the dummy blocks of the second set of dummy blocks is larger than the individual surface areas of each of the dummy blocks of the first set of dummy blocks. | 02-19-2015 |
20150054065 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units. | 02-26-2015 |
20150318367 | Controlling Gate Formation for High Density Cell Layout - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions. | 11-05-2015 |
20150364459 | N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS - The present disclosure provides a semiconductor device. A first active region is formed in a substrate. The first active region is elongated in a first direction in a top view. A first gate is formed over the substrate. The first gate is elongated in a second direction in the top view. A portion of the first gate is located over the first active region. A second gate is formed over the substrate. The second gate is elongated in the second direction in the top view. A portion of the second gate is located over the first active region. The second gate is shorter than the first gate in the second direction. | 12-17-2015 |
20160027898 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature. | 01-28-2016 |
20160042964 | METHOD FOR REMOVING SEMICONDUCTOR FINS USING ALTERNATING MASKS - A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks. | 02-11-2016 |
Patent application number | Description | Published |
20140104876 | LIGHT-GUIDING PLATE, LIGHT-EMITTING MODULE AND DISPLAY APPARATUS - A light-emitting module comprises a light-guiding plate, a plurality of light-guiding elements and a light-emitting unit. The light-guiding plate guides the light direction and has at least an incident surface and two opposite surfaces. The light-guiding elements are disposed on one of the surfaces of the light-guiding plate, and each include a rough surface having a maximum roughness larger than zero micron and less than or equal to 20 microns. The light-emitting unit is disposed to the incident surface of the light-guiding plate. The light emitted by the light-emitting unit is applied to the light-guiding plate, and then, by the guiding of the light-guiding plate and the light-guiding elements, is outputted through one of the surfaces of the light-guiding plate in an alternate form of bright and dark zones. The invention also discloses a light-guiding plate and a display apparatus. | 04-17-2014 |
20140104881 | DISPLAY APPARATUS AND LIGHT-EMITTING MODULE AND LIGHT-GUIDING PLATE THEREOF - A light-emitting module includes a light-guiding plate, a plurality of light-guiding elements and a light-emitting unit. The light-guiding plate can guide the direction of light, and has at least a light input surface and two opposite flat surfaces. The light-guiding elements are disposed at one of the surfaces of the light-guiding plate. By viewing along a direction perpendicular to the surfaces, the shape of each of the light-guiding elements is curve shape with at least one inflection point. The light-emitting unit is disposed adjacent to the light input surface of the light-guiding plate. The light emitted by the light-emitting unit enters the light-guiding plate, is guided by the light-guiding plate and the light-guiding elements, and is outputted through one of the surfaces of the light-guiding plate in an alternating arrangement of bright and dark zones. The invention also discloses a display apparatus and the light-guiding plate. | 04-17-2014 |
20140198279 | DISPLAY APPARATUS HAVING HAZE ELEMENT - A display apparatus comprising a display panel, a light module and a haze element is provided. The light module comprises a light guide plate, a plurality of light guide elements and a first light emitting unit. The light guide plate comprises at least a light-entering surface and two opposite side surfaces. The light guide elements are disposed on at least one of the two side surfaces. The first light emitting unit is disposed on the light-entering surface. The haze element, disposed on the upper surface or the lower surface of the display panel, has a haze ranging between 1% and 10%. After the light emitted from the first light emitting unit enters the light guide plate, the light with the bright state being staggered with the dark state is guided from one of the side surfaces of the light-guiding plate. | 07-17-2014 |
20140204611 | DISPLAY APPARATUS AND LIGHT EMITTING MODULE THEREOF - A display apparatus comprising a display panel and a light emitting module disposed oppositely is provided. The light emitting module comprises a light guide plate, a plurality of light guide grooves and at least a light unit. The light guide plate has at least a light incident surface, a first surface and a second surface opposite to the first | surface. The light guide grooves are disposed on the first surface. Each light guide groove has a bottom, which is the portion of each light guide groove closest to the second surface, wherein the larger the distance from the bottom to the closest light unit, the smaller the distance from the bottom to the second surface. | 07-24-2014 |
20140355113 | DISPLAY APPARATUS AND LIGHT EMITTING MODULE THEREOF - A display apparatus comprising a display panel and a light module is provided. The light module comprises a light guide plate, a plurality of light guide elements and at least a light emitting unit. The light guide plate comprises at least one light incident surface, a first lateral surface and a second lateral surface opposite to the first lateral surface. The plurality of light guide elements are disposed at the first lateral surfaces. A plurality of cross-section parallel to the first light incident surface in the plurality of light guide elements. The farther the distance from the cross-section to the first light incident surface, the larger the area of the cross-section. After emitting from the light emitting unit, the light is guided by the plurality of light guide elements, and emitted from one of the first and the second lateral surfaces of the light guide plate. | 12-04-2014 |
Patent application number | Description | Published |
20130128401 | NETWORK COMMUNICATION DEVICE AND PRINTED CIRCUIT BOARD WITH TRANSIENT ENERGY PROTECTION THEREOF - A network communication device and printed circuit board are provided with transient energy protection. The network communication device includes a transceiver, a transformer, a connector, a spark gap, and a transient energy trigger circuit. The transformer is coupled between the transceiver and the connector. The spark gap and the transient energy trigger circuit are coupled in parallel, between the transformer and a ground end. Alternatively, the spark gap and the transient energy trigger circuit are coupled in parallel, between any two of differential signal lines of the transformer. The spark gap and the transient energy trigger circuit provide a multi-path structure for conducting away the transient energy. A first transient energy is conducted to the ground end through the transient energy trigger circuit, while a second transient energy is conducted to the ground end through the spark gap. | 05-23-2013 |
20140054801 | ELECTRONIC DEVICE - An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively electrically connected to the core circuit. Each pad unit includes at least one pad MOS. A core gate in each core MOS and a pad gate in each pad MOS extend along the same direction or extend parallel with each other. | 02-27-2014 |
20150124361 | ESD PROTECTION CIRCUIT - The disclosure provides an ESD protection circuit. The ESD protection circuit comprises: a clamping unit, a driving unit, a resistance unit, a switch unit, and a capacitance unit. The clamping device is coupled between a first power source and a second power source. The driving unit is coupled between the clamping device and a reference node. The resistance unit is coupled between the first power source and the reference node. The switch unit is coupled to the driving unit via the reference node. The capacitance unit is coupled between the switch unit and the second power source. Under a normal operation condition, the driving unit controls the switch unit to be in an un-conducting status. Under an ESD condition, the driving unit controls the switch unit to be in a conducting status. | 05-07-2015 |