Patent application number | Description | Published |
20100288541 | SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SUBSTRATE , AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE - A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate. | 11-18-2010 |
20100289132 | SUBSTRATE HAVING EMBEDDED SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SAME, AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE - A substrate having single patterned metal layer applied in a package is provided. The substrate includes a first patterned dielectric layer, a patterned metal layer and a second patterned dielectric layer, wherein the patterned metal layer is embedded in the first patterned dielectric layer. Also, the top surfaces of the patterned metal layer and the first patterned dielectric layer lie in the same plane. At least part of the patterned metal layer are exposed from the holes formed on the lower surface of the first patterned dielectric layer, so as to form plural first contact pads for electrical connection downwardly. The second patterned dielectric layer, formed above the patterned metal layer and the first patterned dielectric layer, at least exposes part of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for electrical connection upwardly. | 11-18-2010 |
20100314744 | SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER EXPOSING PATTERNED DIELECTRIC LAYER, CHIP PACKAGE STRUCTURE INCLUDING THE SUBSTRATE, AND MANUFACTURING METHODS THEREOF - A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die. | 12-16-2010 |
20100320610 | SEMICONDUCTOR PACKAGE WITH SUBSTRATE HAVING SINGLE METAL LAYER AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die. | 12-23-2010 |
20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 04-14-2011 |
20110084372 | PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME - A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments. | 04-14-2011 |
20140151876 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 06-05-2014 |
Patent application number | Description | Published |
20110221070 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads. | 09-15-2011 |
20110278734 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 11-17-2011 |
20110278735 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 11-17-2011 |
20110285032 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads. | 11-24-2011 |
20120146108 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate. | 06-14-2012 |
20120184070 | METHOD FOR FORMING CHIP PACKAGE - An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads. | 07-19-2012 |
20120267780 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other. | 10-25-2012 |
20120319297 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions. | 12-20-2012 |
20130307125 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate. | 11-21-2013 |
20140015111 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface. | 01-16-2014 |
20140017828 | HIGH-REFLECTION SUBMOUNT FOR LIGHT-EMITTING DIODE PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a silicon submount for LED packaging. A silicon substrate is provided. A reflection layer is formed on the silicon substrate. Portions of the reflection layer and the silicon substrate are removed to form openings. A wafer backside grinding process is carried out to thin the silicon substrate thereby turning the openings into through silicon vias. An insulating layer is then deposited to cover the reflection layer and the silicon substrate. A seed layer is formed on the insulating layer. A resist pattern is then formed on the seed layer. A metal layer is formed on the seed layer not covered by the resist pattern. The resist pattern is then stripped. The seed layer not covered by the metal layer is then removed. | 01-16-2014 |
20140054786 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess. | 02-27-2014 |
20140199830 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 07-17-2014 |
20140199835 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 07-17-2014 |
20140252659 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad. | 09-11-2014 |
20140312482 | WAFER LEVEL ARRAY OF CHIPS AND METHOD THEREOF - A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided. | 10-23-2014 |
20140332908 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided. | 11-13-2014 |
20140332968 | CHIP PACKAGE - A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided. | 11-13-2014 |
20140332969 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided. | 11-13-2014 |
20140332983 | STACKED CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided. | 11-13-2014 |
20150097299 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided. | 04-09-2015 |
20150162245 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other. | 06-11-2015 |
Patent application number | Description | Published |
20110254820 | ELECTROPHORETIC DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME - An electrophoretic display device and a method for driving the same are disclosed. The electrophoretic display device includes a plurality of pixels, a first electrode layer, a second electrode layer, a driving voltage generating unit, and an electrophoretic layer disposed between the first electrode layer and the second electrode layer. The driving voltage generating unit is capable of providing a plurality of various driving voltages to drive charged particles in the electrophoretic layer, so as to increase the number of gray levels displayed by the electrophoretic display device. | 10-20-2011 |
20120032930 | DUAL-VIEW DISPLAY DEVICE AND DISPLAY METHOD THEREOF - A dual-view display device and a display method thereof are disclosed. The dual-view display device includes a backlight module, an optical film, a liquid crystal display panel, and a main control unit. The backlight module includes a light guide plate, a left light source, and a right light source. The optical film is disposed in front of the backlight module. The liquid crystal display panel is disposed in front of the optical film. The main control unit is electrically coupled to the left light source, the right light source, and the liquid crystal display panel. The main control unit transmits an image data to the liquid crystal display panel and controls the left and right light sources according to the image data, so as to control the liquid crystal display panel adaptively to display an identical image, one view image, or dual-view images. | 02-09-2012 |
20120032931 | DUAL-VIEW DISPLAY DEVICE AND DISPLAY METHOD THEREOF - A dual-view display device and a display method thereof are disclosed. The dual-view display device includes a backlight module, an optical film, a liquid crystal display panel, and a main control unit. The backlight module includes a light guide plate, a left light source, and a right light source. The optical film is disposed in front of the backlight module. The liquid crystal display panel is disposed in front of the optical film. The main control unit is electrically coupled to the left light source, the right light source, and the liquid crystal display panel. The main control unit transmits an image data to the liquid crystal display panel and controls the left and right light sources according to the image data, so as to control the liquid crystal display panel adaptively to display an identical image, one view image, or dual-view images. | 02-09-2012 |
20120120039 | Driving System for Display and Method of the Same - The present invention discloses a driving system and the method thereof for a display system, and particularly for the display system with a bi-stable display. The driving system of the present invention has the advantage of requiring less memory capacity than that of traditional driving systems. The driving system of the present invention reads one frame data at one time and will clear the current frame before displaying a new frame. Owing to the current frame being cleared before a new frame being updated, the driving system needs not to record the difference of gray level between the two frames and thereby reduces the requirement of memory capacity. | 05-17-2012 |
20130093716 | Capacitive Touch Panel and Touch Detection Method of the Same - A capacitive touch panel comprises a touch detection array having rows of first direction detection units and columns of second direction detection units, shared scan lines, independent scan lines and a driver control module. The first direction detection units are divided into a first group and a second group of rows arranged in an alternating manner. Each shared scan line is connected to one row of the first direction detection units in the first group and one column of the second direction detection units. Each independent scan line is connected to one row of the first direction detection units or one column of the second direction detection units that is not connected to the shared scan lines. The driver control module is connected to the shared scan lines and the independent scan lines to perform scanning processes to detect a touch input. A touch detection method is also disclosed. | 04-18-2013 |
20130241961 | ELECTROPHORETIC DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME - Disclosed are an electrophoretic display device and a method for driving the same. The electrophoretic display device includes a first electrode layer, a second electrode layer, an electrophoretic layer, and a controller. The first electrode layer includes a plurality of pixels formed thereon. The electrophoretic layer is disposed between the first electrode layer and the second electrode layer. The controller looks up a write-in gray level data of each pixel in each frame from a lookup table. The lookup table records the write-in gray level data of each pixel in each frame when a gray level of each pixel is changed from a reference gray level to a required gray level. The present invention is capable of decreasing the lookup table size. | 09-19-2013 |
20130313098 | ELECTRODE ARRAY OF TOUCH PANEL - Disclosure is an electrode array of a touch panel, which includes a plurality of rhombus-shaped electrodes, dumbbell-shaped electrodes, and bridge wires. The rhombus-shaped electrodes are arranged along a first direction and interconnected in the first direction. The dumbbell-shaped electrodes are arranged along a second direction. Each dumbbell-shaped electrode has a first enlarged part, a second enlarged part, and a narrow part. Here, each rhombus-shaped electrode is disposed between two adjacent dumbbell-shaped electrodes along the second direction. The bridge wires are used for electrically coupling the two first enlarged parts and the two second enlarged parts of the two adjacent dumbbell-shaped electrodes, respectively. The production reliability of the present invention is increased according to the dumbbell-shaped electrodes. | 11-28-2013 |
Patent application number | Description | Published |
20130063013 | Combination Drawer with Adjustable Dividing Function - A combination drawer includes a drawer body, at least one dividing unit mounted in the drawer body, and at least one retractable member slidably mounted on the dividing unit. Thus, the retractable member co-operates with the dividing unit to fit the length of the drawer body so that the total length of the retractable member and the dividing unit can be adjusted to fit the drawer body of different sizes, thereby enhancing the versatility of the combination drawer. | 03-14-2013 |
20130063014 | Combination Drawer with Adjustable Dividing Function - A combination drawer includes a drawer body, two support bars located at two opposite ends of the drawer body, at least one dividing unit mounted in the drawer body and disposed between the support bars, at least two upper retractable members retractably mounted on two opposite ends of the dividing unit and connected with the support bars respectively, and at least two lower retractable members retractably mounted on the two opposite ends of the dividing unit and each abutting an inner side of the drawer body. Thus, the lower retractable members are movable relative to the dividing unit to co-operate with the dividing unit so as to fit the length of the drawer body, such that the total length of the dividing unit and the lower retractable members can be adjusted to fit the drawer body of different sizes. | 03-14-2013 |
20130181590 | Combination Drawer - A combination drawer includes a front panel module, a rear panel, two side panel modules and a plurality of bottom panels. The front panel module includes a first outer plate combined with a first inner plate. The front panel module has two opposite ends each provided with a first bent portion which has at least one first connecting section. The rear panel has two opposite ends each provided with a second bent portion which has at least one second connecting section. Each of the side panel modules includes a second outer plate combined with a second inner plate. Each of the side panel modules has two opposite end faces each provided with at least one third connecting section connected with the first connecting section of the front panel module and the second connecting section of the rear panel respectively. | 07-18-2013 |
20140167583 | Combination Cabinet with Foldable Door - A combination cabinet includes at least one pair of door frames, at least one separation bar mounted between the door frames, a pair of fixing seats mounted on the separation bar, and a plurality of pivot pieces each mounted in a respective one of the door frames and each pivotally connected with a respective one of the fixing seats. The separation bar has an upper end and a lower end each provided with a slot for mounting a respective one of the fixing seats. Each of the fixing seats has a side provided with an insert inserted into the respective slot of the separation bar. Thus, the separation bar closes the gap between the door frames during pivotal movement of the door frames, thereby preventing a person from being clamped or hurt by the gap between the door frames. | 06-19-2014 |
20160095431 | Furniture Fixture for Cabinet - A fixture for a piece of furniture includes at least one post, at least one mounting member, and at least one fixing unit. The post is provided with at least one fixing track which has an upper narrow portion and an inner wide portion. The fixing unit includes an abutting member secured on the fixing track, and a fastening member connected with the mounting member and the abutting member to attach the mounting member to the post. The abutting member has a width slightly smaller than the upper narrow portion of the fixing track and has a length slightly greater than the inner wide portion of the fixing track. Thus, the mounting member is located on any proper position of the fixing track by fixing of the fixing unit so that the mounting member is affixed to the post. | 04-07-2016 |