Chen-Ming
Chen-Ming Chan, New Taipei City TW
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20130075550 | SUPPORTING ASSEMBLY FOR ELECTRONIC DEVICE - A supporting assembly is disposed to a case of an electronic device. A window is formed on the case for communicating an inner surface and an outer surface of the case. The supporting assembly includes a fixed part, a latching post, and a support body. The fixed part is disposed to the inner surface. The latching post includes a fixing end and an inserting end. The fixing end runs through the window and is fixed to the fixed part. A first stopping block is disposed to the inserting end. The support body includes a supporting side and a combination side. A combination hole is formed at the combination side for the inserting end to insert therein. The support body further includes a second stopping block protrudly disposed in the combination hole, for stopping the first stopping block to prevent the inserting end from escaping from the combination hole. | 03-28-2013 |
Chen-Ming Chang, Taipei TW
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20100077581 | Process for producing piezoelectric ceramic devices - An improved process for producing a piezoelectric ceramic device is disclosed, wherein the process includes the following steps: securing a metal plate in a mold cavity body by maintaining a binding area on a top surface of the metal plate, and that the top surface other than the binding area is enveloped, confined and secured; coating a metal paste on the binding area; placing a piezoelectric ceramic powder on the metal paste; pressing a pressing pillar on the piezoelectric ceramic powder; securing the pressing pillar in position; heating the mold cavity body so as to sinter the piezoelectric ceramic powder as a sintered body, and heating the mold cavity body so as to treat the sintered body to become a not-yet polarized piezoelectric ceramic sheet. Therefore, the same mold is employed for the piezoelectric ceramic powder sintering, the heat treatment, and the positioning and binding to the metal plate. | 04-01-2010 |
20110265021 | TOUCHPAD CONTROLLING METHOD AND TOUCH DEVICE USING SUCH METHOD - A touchpad controlling method and a touch device using such a method are provided. The touch device is applied to an electronic appliance. The touch device includes a touchpad and a coordinate transformation program. The touchpad is used for detecting a number of touching points in response to the touching gesture on the touchpad and the position of each touching point. If the number of touching points is equal to 1, the electronic appliance is operated in a relative coordinate mode. Whereas, if the number of touching points is greater than 1, the electronic appliance is operated in an absolute coordinate mode. | 10-27-2011 |
20150253867 | KEYBOARD DEVICE WITH TOUCH CONTROL FUNCTION - A keyboard device with a touch control function is provided. The keyboard device includes plural keys, plural first touch detectors, a second touch detector, and a controlling unit. The plural first touch detectors arranged in a row and located under a space key. The second touch detector is located under a neighboring key around the space key. If the space key and the neighboring key around the space key are sequentially touched by the user, the controlling unit sequentially receives plural first touch signal and a second touch signal. Consequently, the controlling unit issues a touch command to a computer host. Consequently, for generating the touch command, it is not necessary to change the customary gesture of the user of operating the keyboard device. | 09-10-2015 |
Chen-Ming Chen, Taichung City TW
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20130256706 | PIXEL ARRAY AND DISPLAY PANEL - A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same. | 10-03-2013 |
20150179671 | PIXEL ARRAY AND DISPLAY PANEL - A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same. | 06-25-2015 |
Chen-Ming Chen, Hsinchu TW
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20090051639 | Method and device for reducing voltage stress at bootstrap point in electronic circuits - A discharging device is used to reduce the voltage level at a bootstrap point in an electronic circuit such as a shift register circuit. In such a circuit, a first transistor in a conducting state receives an input pulse and conveys it to the gate terminal of a second transistor, causing the second transistor to be in a conducting state. This gate terminal is known as a bootstrap point. After receiving the input pulse, an output pulse is produced at one drain/source terminal of the second transistor. During the time period of the output pulse, the first transistor is in a non-conducting state and the voltage level at the bootstrap point is high, imposing a stress upon the first transistor. A discharging circuit consisting of at least one transistor is coupled to the bootstrap point in order to reduce the voltage level at the output pulse period. | 02-26-2009 |
20100067646 | SHIFT REGISTER WITH EMBEDDED BIDIRECTIONAL SCANNING FUNCTION - A shift register comprises a plurality of stages, {S | 03-18-2010 |
Chen-Ming Chen, Hsin-Chu TW
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20090206909 | BIDIRECTIONAL CONTROLLING DEVICE FOR INCREASING RESISTANCE OF ELEMENTS ON VOLTAGE STRESS - A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets. | 08-20-2009 |
20110169747 | Touch Detection Method - A touch detection method is adapted for a display apparatus. The display apparatus comprises a first gate line, a sensor pad and a second gate line adjacent to the first gate line. The sensor pad is electrically coupled to the first gate line. The touch detection method comprises steps of: enabling the first gate line; and detecting whether the sensor pad is touched before enabling the second gate line. Therein, a partial overlapped time exists between a subsequent enable period for enabling the second gate line and an enable period for enabling the first gate line. | 07-14-2011 |
20130127801 | DISPLAY PANEL - A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly. | 05-23-2013 |
20130155035 | METHOD FOR DRIVING PIXEL CIRCUITS - A method for driving a pixel circuit, which is adapted to drive a first pixel circuit coupled to a first gate line and a second pixel circuit coupled to a second gate line, is disclosed. The first pixel circuit receives display data before the second pixel circuit does. The method provides only one first enable pulse to the first gate line in a frame, and provides a second enable pulse and a third enable pulse to the second gate line in the same frame. The starting time of the second enable pulse is in an enabled time period of the first enable pulse, and the enabled time period of the third enable pulse is after the enabled time periods of the first and second enable pulses. | 06-20-2013 |
20140132651 | DISPLAY AND METHOD OF GENERATING AN IMAGE WITH UNIFORM BRIGHTNESS - A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line. | 05-15-2014 |
20140355731 | SHIFT REGISTER CIRCUIT AND DRIVING METHOD THEREOF | 12-04-2014 |
Chen-Ming Chiu, Hsin-Chu City TW
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20080232099 | HOLDER STRUCTURE - The present invention discloses a holder structure for retaining at least one lamp and associated wire within a backlight module, which includes a main body, a reflector, and a first groove formed on an external sidewall of the main body. The main body has at least one first orienting slot for accommodating the lamp therein, and a second orienting slot for accommodating a high-voltage power wire therein. Said first groove communicates with the first and second orienting slots to divide a lateral slot wall of each of the first and second orienting slots into two opposite flexible walls which can provide flexibility required for assembly of the lamp and associated wire. Each two opposite flexible walls have two protrusions respectively formed on the outsides thereof for hooking with corresponding openings defined on the reflector, whereby the lamp and power wires are able to be firmly retained in the associated slots, respectively. | 09-25-2008 |
Chen-Ming Hsiao, Sinying City TW
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20100121068 | Process for preparing rabeprazole sodium - The present invention provides a process for preparing the amorphous rabeprazole sodium. The process comprises the following steps: (a) Contacting rabeprazole sodium compound with a solvent system to thereby obtain a clear solution under a first temperature, wherein said solvent system is a mixture of at least two categories of organic solvents; (b) Stirring said clear solution of step (a) under a second temperature for a certain time period to obtain a solution containing resultant separated solid, wherein said second temperature is equal to or lower than said first temperature; (c) Filtering said solution containing resultant separated solid obtained from step (b) to obtain a wet solid; and (d) Drying said wet solid to obtain an amorphous rabeprazole sodium compound. | 05-13-2010 |
20110092507 | Process for preparing R-(+)-3-morpholino-4-(3- tert-butylamino-2-hydroxypropoxy)-1,2,5-thiadiazole - The present invention provides a process for preparing optically active timolol. The process comprises the following steps. Firstly, reacting 3-hydroxy-4-morpholino-1,2,5-thiadiazole with an optically active epichlorohydrin in the presence of a solvent system, which has a first volume and a catalyst optionally in the presence of a suitable base to obtain an optically active intermediate product. Secondly, treating the optically active intermediate product with a solution, which has a second volume and comprises tert-butylamine to obtain an optically active timolol. The solvent system used in the first step can be an amide solvent, sulfoxide solvent, cyclic hydrocarbon solvent, ketone solvent, or a heterocyclic solvent. The catalyst used in the first step can be an alkali metal hydroxide, alkali metal carbonate, alkali metal hydrogen carbonate, piperidine, pyridine, triethylamine, potassium hydroxide, sodium hydroxide, potassium carbonate, and other heterocyclic bases. | 04-21-2011 |
Chen-Ming Hsu, New Taipei City TW
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20140071605 | PROTECTIVE COVER FOR A TABLET COMPUTER - Aspects of the invention relate to an apparatus including a housing and a slot disposed in the housing, the slot configured to hold an input device in a plurality of upright configurations including at least a forward-facing upright configuration such that the input device faces the front portion of the housing, and at least a backward-facing upright configuration such that the input device faces the back portion of the housing. The slot can be overmolded with a rubber compound (e.g. silicon-based) and configured to provide an improved coefficient of friction to reduce slippage of the input device when held in the slot. In some aspects, the housing includes a surface, and the overmolded portion of the slot can protrude above the surface of the housing. | 03-13-2014 |
Chen-Ming Hsu, Sinshih Township TW
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20120004880 | Temperature Sensor and Temperature Sensing Method - A temperature sensor is provided. The temperature sensor includes: a temperature sensing unit for sensing a temperature and outputting a temperature sensing signal; an analog-to-digital converter (ADC), coupled to the temperature sensing unit, for converting the temperature sensing signal to a digital value, having an ADC output range; a calibration unit, coupled to the ADC, for correlating the ADC output range with at least one temperature range; a memory unit, coupled to the calibration unit, recording the ADC output range, and the at least one temperature range, and the correlation therebetween. | 01-05-2012 |
Chen-Ming Hsu, Taipei TW
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20150342626 | CALCULUS AIMING AND LOCKING SYSTEM - The invention is a calculus aiming and locking system that is an application computer system and comprises a calculus locating module, an aiming and locking and emission control module, and a shockwave generation module. The calculus locating module acquires and calculates a calculus image of a calculus and the aiming and locking and emission control module determines whether to trigger a shockwave generation module to control a shockwave emission device to emit energy at an effective aiming area according to whether the calculus coordinate is within the effective aiming area. The invention renders the calculus hit rate 100% when the shockwave emission device emits energy, which may save energy substantially and avoid causing injuries to the normal tissue of the patient requiring extracorporeal shockwave lithotripsy treatment. | 12-03-2015 |
Chen-Ming Hu, Pingtung County TW
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20130153949 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer. | 06-20-2013 |
20130299870 | LIGHT EMITTING DEVICE - A light emitting device is provided. A light emitting device that includes a substrate, a first electrode, a passivation layer, a second electrode, and a light emitting layer is provided. The first electrode is disposed on the substrate and includes a first patterned conductive layer. The first patterned conductive layer includes an alloy containing a first metal and a second metal. The passivation layer is at least disposed on a side surface of the first electrode and includes a compound of the second metal. Here, a work function of the compound of the second metal ranges from about 4.8 to about 5.5. The second electrode is disposed on the first electrode. The light emitting layer is disposed between the first electrode and the second electrode. | 11-14-2013 |
20130309787 | MANUFACTURING METHOD OF LIGHT EMITTING DEVICE - A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer. | 11-21-2013 |
Chen-Ming Huang, Taipei City TW
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20150255563 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MULTI-LAYER HARD MASK - A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon. | 09-10-2015 |
20160099179 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed. | 04-07-2016 |
20160141387 | FIN SHAPED STRUCTURE AND METHOD OF FORMING THE SAME - A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure. | 05-19-2016 |
Chen-Ming Huang, Tainan City TW
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20160104713 | WING-TYPE PROJECTION BETWEEN NEIGHBORING ACCESS TRANSISTORS IN MEMORY DEVICES - A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines. | 04-14-2016 |
Chen-Ming Huang, Hsin-Chu TW
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20140179071 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 06-26-2014 |
20140246758 | NITROGEN-CONTAINING OXIDE FILM AND METHOD OF FORMING THE SAME - A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %). | 09-04-2014 |
20150179502 | Two-Step Shallow Trench Isolation (STI) Process - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 06-25-2015 |
Chen-Ming Huang, Hsinchu City TW
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20100197141 | NOVEL SELF-ALIGNED STATIC RANDOM ACCESS MEMORY (SRAM) ON METAL GATE - A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions. | 08-05-2010 |
20100234975 | ADVANCED PROCESS CONTROL FOR GATE PROFILE CONTROL - A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range. | 09-16-2010 |
20100270636 | ISOLATION STRUCTURE FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated image sensor includes an isolation structure passing through a substrate, a sensor element formed overlying the front surface of the substrate, and a color filter formed overlying the back surface of the substrate. | 10-28-2010 |
20100279459 | METHOD FOR REDUCING CONTACT RESISTANCE OF CMOS IMAGE SENSOR - A method for performing a CMOS Image Sensor (CIS) silicide process is provided to reduce pixel contact resistance. In one embodiment, the method comprises forming a Resist Protect Oxide (RPO) layer on the CIS, forming a Contact Etch Stop Layer (CESL), forming an Inter-Layer Dielectric (ILD) layer, performing contact lithography/etching, performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at pixel contact hole area, performing contact filling, and defining the first metal layer. The Resist Protect Oxide (RPO) layer can be formed without using a photo mask of Cell Resist Protect Oxide (CIRPO) photolithography for pixel array and/or without silicide process at pixel array. The method can include implanting N+ or P+ for pixel contact plugs at the pixel contact hole area. The contact filling can comprise depositing contact glue plugs and performing Chemical Mechanical Polishing (CMP). | 11-04-2010 |
20110108940 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 05-12-2011 |
20120288982 | METHOD FOR REDUCING CONTACT RESISTANCE OF CMOS IMAGE SENSOR - This description relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at the pixel contact hole area and performing contact filling. This description also relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes implanting N+ or P+ for pixel contact plugs at a pixel contact hole area, performing Physical Vapor Deposition (PVD) at pixel contact hole area, annealing for silicide formation at the pixel contact hole area, performing contact filling and depositing a first metal film layer, wherein the first metal film layer links contact holes for a source, a drain, or a poly gate of a CMOS device. | 11-15-2012 |
20130001725 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 01-03-2013 |
20130076385 | Semiconductor Test Structures - A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension. | 03-28-2013 |
20130093036 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 04-18-2013 |
20130107248 | ENHANCED DEFECT SCANNING | 05-02-2013 |
20140054653 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel. | 02-27-2014 |
20140151835 | BACKSIDE ILLUMINATED IMAGE SENSORS AND METHOD OF MAKING THE SAME - A backside illuminated image sensor includes a substrate with a substrate depth, where the substrate includes a pixel region and a peripheral region. The substrate further includes a front surface and a back surface. The backside illuminated image sensor includes a first isolation structure formed in the pixel region of the substrate, where a bottom of the first isolation structure is exposed at the back surface of the substrate. The backside illuminated image sensor includes a second isolation structure formed in the peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. The backside illuminated image sensor includes an implant region adjacent to at least a portion of sidewalls of each isolation structure in the pixel region. | 06-05-2014 |
20140162534 | POLISHING SYSTEM AND POLISHING METHOD - A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. | 06-12-2014 |
20140203282 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 07-24-2014 |
20140206113 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 07-24-2014 |
20150111334 | METHOD OF MAKING BACKSIDE ILLUMINATED IMAGE SENSORS - A method of making a backside illuminated image sensor includes forming a first isolation structure in a pixel region of a substrate, where a bottom of the first isolation structure is exposed at a back surface of the substrate. The method further includes forming a second isolation structure in a peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. Additionally, the method includes forming an implant region adjacent to at least a portion of sidewalls of the first isolation structure, where the portion of the sidewalls is located closer to the back surface than a front surface of the substrate, and where the second isolation structure is free of the implant region. | 04-23-2015 |
Chen-Ming Huang, Hsinch City TW
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20140030866 | METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER - A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided. | 01-30-2014 |
Chen-Ming Hung, Zhubei City TW
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20130221995 | SENSE AMPLIFIER - An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device. | 08-29-2013 |
20140061851 | METAL-VIA FUSE - The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window. | 03-06-2014 |
20140369105 | GENERATING OUTPUT SIGNAL DURING READ OPERATION - A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell. | 12-18-2014 |
20160035527 | FUSE STRUCTURE - A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction. The fuse line has a first end portion, a second end portion opposite the first end portion, and a fuse link portion connecting the first end portion and the second end portion. The first conductive layer also comprises lines parallel to the fuse line, the lines being aligned in the first direction and being separated from one another by a first distance measured in the first direction. The fuse structure also comprises a second conductive layer on a second level different from the first level and coupled with the first conductive layer. The second conductive layer has parallel lines extending in a second direction, the parallel lines being separated by a second distance measured in a third direction orthogonal to the second direction. | 02-04-2016 |
Chen-Ming Lai, Tainan City TW
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20120025369 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor element, a plurality of element contacts and a molding compound. The substrate includes a passivation layer and a plurality of substrate pads. Each substrate pad includes a protrusion and an embedded portion. The embedded portion is embedded in the passivation layer, and the protrusion projects from the passivation layer. The semiconductor element includes a plurality of under bump metallurgies (UBM) with recesses. The ratio of the width of each recess to the first width of the protrusion is larger than 1. The element contacts connect the UBM and the substrate pads. The molding compound covers the semiconductor element. | 02-02-2012 |
20120032351 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor device, a plurality of element contacts, a molding compound and a plurality of substrate contacts. The substrate has opposite to the first surface the first surface and the second surface. The semiconductor device is disposed on the first surface. The element contacts electrically connect the substrate and the semiconductor device. The molding compound encapsulates the semiconductor device and a portion of the molding compound is located between the semiconductor device and the first surface, wherein the molding compound includes a plurality of fillers, the fillers amount to 85-89% of the molding compound and the sizes of the fillers range between 18 and 23 micrometers. The substrate contacts are formed on the second surface. | 02-09-2012 |
Chen-Ming Lee, Santa Ana, CA US
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20120066311 | NETWORK CONNECTION ESTABLISHMENT AND DATA TRANSMISSION METHOD - The present innovation discloses a network communication establishment method between a portable device and a computer. The major feature of the present innovation is that the parameters are transmitted via the email and after the connection is established, the commands or requests for data transmission are still transmitted via email. As to the data under transmission, it is transmitted by peer to peer (P2P) technology. In another embodiment, the data may also be transmitted via email. | 03-15-2012 |
20120066318 | DATA TRANSMISSION METHOD - The present invention discloses a data transmission method for a first electronic device and a second electronic device. The method includes the steps of finding a first available port of the first electronic device, finding a second available port of the second electronic device, transforming a first data into a second data, wherein a format of the second data is an XML format, and transmitting the second data to the first electronic device or the second electronic device via the first available port or the second available port. | 03-15-2012 |
Chen-Ming Lee, Taoyuan County TW
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20150243565 | METHODS OF FORMING LOW RESISTANCE CONTACTS - Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings. | 08-27-2015 |
20160035629 | METHODS OF FORMING LOW RESISTANCE CONTACTS - Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings. | 02-04-2016 |
Chen-Ming Lee, Yangmei City TW
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20160141384 | MASK-LESS DUAL SILICIDE PROCESS - A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions. | 05-19-2016 |
Chen-Ming Li, Bade City TW
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20120062212 | Zero Bias Power Detector - A zero bias power detector comprising a zero bias diode and an output boost circuit is provided. The output boost circuit comprises a zero bias transistor. The zero bias diode is not biased but outputs a rectifying signal according to a wireless signal. The zero bias transistor, not biased but coupled to the zero bias diode, is used for enhancing the rectifying signal. | 03-15-2012 |
20120139805 | ANTENNA STRUCTURE AND MULTI-BEAM ANTENNA ARRAY USING THE SAME - An antenna structure comprises a substrate, a first antenna unit and a second antenna unit. The substrate comprises a first surface and a second surface opposing the first surface. The first antenna unit is disposed on the first surface, and comprises at least a first slot with a wider inside and narrower outside at the edge of the first antenna unit. The second antenna unit is disposed on the second surface, and is connected to the first antenna unit through a hole in the substrate. The radius of the at least one first slot is one-fourth the wavelength of the central frequency of the antenna structure. | 06-07-2012 |
Chen-Ming Lin, Minxiong Township TW
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20110259059 | ELECTRIC DOOR LOCK - An electric door lock including: a lock housing; an operating member having a holding part and a shaft part, the shaft part able to be placed in the lock housing, the shaft part connected to the holding part, the holding part defined as a long axis; a cog wheel able to be placed in the lock housing, the cog wheel having at least one bump; a coupling plate installed on the shaft part of the operating member, the coupling plate having at least one bulge and one protruding part, with the protruding part and the long axis of the holding part designed to move in alignment with each other; a motor placed in the lock housing; three sensor switches set separately in the lock housing; operating the motor causing the bump of the cog wheel to rotate and push the bulge of the coupling plate, so that the protruding part of the coupling plate of the electric door lock installed in the required position on a left-hand door or right-hand door, selectively touches the two sensor switches adjacent to each other, so as to reach the correct unlocked position or locked position. | 10-27-2011 |
Chen-Ming Wang, Kaohsiung City TW
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20130259358 | SYSTEM AND METHOD FOR ALIGNMENT IN SEMICONDUCTOR DEVICE FABRICATION - A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes | 10-03-2013 |
20140253901 | Two-Dimensional Marks - A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions. | 09-11-2014 |