Chen, Hsin-Chu
Benhon Chen, Hsin-Chu TW
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20110002112 | Display Device with Panel Positioning Structure and Method for Manufacturing the Same - A panel display and a method for manufacturing the same are provided. The panel display includes a frame, an elastic pad, and a display panel. The frame has a supporting tray and a side wall which perpendicularly extends from the end of the supporting tray. A groove is formed on the supporting tray adjacent to the foot of the side wall. One end of the elastic pad is located within the groove while the other end leans on the side wall before the display panel is configured with the frame. When entering the display panel into the frame, the edge of the display panel compels the elastic pad to bend and form a bottom portion and a side portion. The bottom portion is accommodated in the groove while the side portion is compressed by the edge of the display panel and lies on the side wall. | 01-06-2011 |
Ben-Hon Chen, Hsin-Chu TW
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20100097784 | Lamp Positioning Device and the Backlight Module Using the Same - The present invention provides a lamp positioning device and a backlight module using the lamp positioning device for holding lamps. The lamp positioning device includes an upper arm and a lower arm, wherein a holding space is formed between the upper arm and the lower arm for accommodating the lamp. Furthermore, at least one of the upper arm and the lower arm has elasticity and thus can provide the lamp with resistance against shock in order to avoid being cracked or shattered. | 04-22-2010 |
Bing-Hung Chen, Hsin-Chu TW
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20110007258 | Display Panel and Method for Fabricating the Same - A display panel includes a first substrate, a second substrate, a seal and at least one block. The second substrate is disposed opposite to the first substrate. The seal is disposed between the first substrate and the second substrate and has a first side and a second side. The first side has at least one liquid crystal inlet and connects in approximately perpendicular to the second side. The block is disposed between the first substrate and the second substrate and adjoins the first side of the seal. The block is disposed between the liquid crystal inlet and the connection of the first side and the second side. A method for fabricating a display panel is also disclosed herein | 01-13-2011 |
20120175057 | Display Panel and Method for Fabricating the Same - A method for fabricating a display panel is provided. The method includes steps of: disposing a seal on a first substrate, in which a first side of the seal connects in approximately perpendicular to a second side of the seal and has at least one liquid crystal inlet; forming at least one block on the first substrate and between the liquid crystal inlet and the connection of the first side and the second side of the seal, in which there is a space between the block and the first side of the seal when the block is formed; and pressing a second substrate against the first substrate having the seal and the block thereon, such that the block adjoins the first side of the seal after the second substrate is pressed. | 07-12-2012 |
Chao-Shun Chen, Hsin-Chu TW
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20090231549 | BEAM COMBINING DEVICE AND PROJECTOR HAVING SUCH BEAM COMBINING DEVICE - A beam combining device and a projector having such a beam combining device are provided. The projector includes a first color light source, a second color light source, a third color light source, a beam combining device, a light valve and a projection unit. The first color light source, the second color light source and the third color light source respectively emit first, second and third color beams. The beam combining device includes a polarization state converting module, a color separation unit and a polarization beam splitter. The optical path lengths of the first color beam emitted from the first color light source to the polarization beam splitter, the second color beam emitted from the second color light source to the polarization beam splitter, and the third color beam emitted from the third color light source to the polarization beam splitter are equal. | 09-17-2009 |
20110002051 | Fixed focus lens and imaging system - A fixed-focus lens capable of imaging a light valve disposed at a reduced side onto a magnified side is provided. The fixed-focus lens includes a first lens group, a second lens group, and a free form reflective mirror. The first lens group is disposed in the light path between the reduced side and the magnified side. The second lens group is disposed in the light path between the first lens group and the magnified side and includes a first free form lens. The free form reflective mirror is disposed in the light path between the second lens group and the magnified side. An imaging surface imaged from the light valve by the fixed-focus lens is a curved surface. An imaging system using the fixed-focus lens is also provided. | 01-06-2011 |
Che-Hsien Chen, Hsin-Chu TW
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20110090199 | Display Panel Driving Circuit, Display Panel, and Driving Method thereof - By following properties that there is coupled noise, which is coupled from a display panel, within at least one common voltage used on the display panel, the at least one common voltage is fed-back into a pixel electrode driving module, and driving voltages are generated accordingly, so that the generated driving voltages carry noises closes to coupled noises of the display panel. As a result, while the driving voltages carrying noises from the at least one common voltage, the pixel electrode driving module is capable of driving a corresponding pixel electrode with a stable voltage difference, and thereby capable of relieving horizontal crosstalk and raising a display quality of the display panel. | 04-21-2011 |
20120062526 | DRIVING CIRCUIT OF A LIQUID CRYSTAL DEVICE AND RELATED DRIVING METHOD - A driving circuit of an LCD device and related driving method is provided. The driving circuit includes a thermal sensor and a power IC. The thermal sensor is configured to detect the operational temperature of the LCD device, thereby generating a corresponding thermal signal. The power IC is configured to provide a plurality of clock signals for driving a gate driver of the LCD device, and adjust the effective pulse widths of the plurality of clock signals according to the thermal signal. | 03-15-2012 |
20120105512 | METHOD FOR CONTROLLING GATE SIGNALS AND DEVICE THEREOF - A method for controlling gate signals of a liquid crystal display (LCD), including generating gate signal with a modulated pulse width according to the gate signal with a default pulse width; when the LCD is booting up, outputting the gate signal with the modulated pulse width; and when a backlight module of the LCD is turned on, switching the gate signal with the modulated pulse width to the gate signal with the default pulse width. This way, the pulse width of the gate signal is increased after the LCD is boot up and before the backlight module is turned on, enabling the LCD to be boot properly in low temperature, without the need to raise the voltage level of the gate signal. | 05-03-2012 |
Chen-Lung Chen, Hsin-Chu TW
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20110148816 | OPTICAL TOUCH DISPLAY APPARATUS - An optical touch display apparatus including a backlight module, a display panel, and at least an optical detector is provided. The backlight module is capable of providing a visible beam and an invisible beam. The display panel is disposed at one side of the backlight module. A sensing space is located in front of the display panel, and the display panel is located between the backlight module and the sensing space. The visible beam and the invisible beam are capable of passing through the display panel and then being transmitted to the sensing space. The optical detector is disposed outside the display panel for sensing the invisible beam from the sensing space. | 06-23-2011 |
20110148818 | OPTICAL TOUCH DISPLAY APPARATUS - An optical touch display apparatus includes the following. A light distribution adjustment device is disposed in a transmission path of a visible beam emitted by a visible light emitting device. A non-visible light guide module includes a light guide unit and a dichroic unit. A light guide unit is disposed in the transmission path of the visible beam from the light distribution adjustment device. The dichroic unit is disposed on a surface of the light guide unit. A non-visible light emitting device is disposed beside a side surface of the light guide unit. A display panel is disposed beside the light distribution adjustment device. A sensing space is located in front of the display panel, and the display panel is disposed between the light distribution adjustment device and the sensing space. An optical detector is disposed outside the display panel. | 06-23-2011 |
20130223094 | DISPLAY MODULE - A display module has a display panel and a backlight module disposed on one side of the display panel. The backlight module includes a heat sink, a light bar, a light guide plate, a first reflective sheet, and a second reflective sheet. The light bar abuts against one side of the heat sink. The first reflective sheet is disposed adjacent to a bottom surface of the light guide plate, and the second reflective sheet is disposed adjacent to an edge of a light-emitting surface of the light guide plate. The second reflective sheet has a first part and a second part forming an included angle with the first part, the first part is attached to the heat sink or the light bar, and the second part overlaps a part of the light-emitting surface of the light guide plate. | 08-29-2013 |
Chen-Min Chen, Hsin-Chu TW
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20090115390 | POWER CONVERTER WITH PROTECTION MECHANISM FOR DIODE IN OPEN-CIRCUIT CONDITION AND PULSE-WIDTH-MODULATION CONTROLLER THEREOF - A power converter with a protection mechanism for a diode in an open-circuit condition includes a DC to Dc (DC/DC) conversion circuit, a detection and protection circuit, a pulse-width-modulation (PWM) signal generator, and a logic gate. The detection and protection circuit is used for detecting an open-circuit condition of the diode of the DC/DC conversion circuit. The logic gate receives an output signal of the detection and protection circuit and a PWM signal outputted by the PWM signal generator. When the diode is in an open-circuit condition, the PWM signal cannot be transmitted to a power switch of the DC/DC conversion circuit due to the output signal of the detection and protection circuit. | 05-07-2009 |
20110133714 | POWER CONVERTER WITH PROTECTION MECHANISM FOR DIODE IN OPEN-CIRCUIT CONDITION AND PULSE-WIDTH-MODULATION CONTROLLER THEREOF - A power converter with a protection mechanism for a diode in an open-circuit condition includes a DC to Dc (DC/DC) conversion circuit, a detection and protection circuit, a pulse-width-modulation (PWM) signal generator, and a logic gate. The detection and protection circuit is used for detecting an open-circuit condition of the diode of the DC/DC conversion circuit. The logic gate receives an output signal of the detection and protection circuit and a PWM signal outputted by the PWM signal generator. When the diode is in an open-circuit condition, the PWM signal cannot be transmitted to a power switch of the DC/DC conversion circuit due to the output signal of the detection and protection circuit. | 06-09-2011 |
Chia-Kai Chen, Hsin-Chu TW
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20100013001 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY AND STRUCTURE THEREOF - A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer. | 01-21-2010 |
Chia-Tien Chen, Hsin-Chu TW
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20090244722 | TURNING MECHANISM - A turning mechanism is adapted to a projector including a base and a zoom lens set in a base for turning a zoom bar of the zoom lens. The turning mechanism includes a fixed element and a movable element. The fixed element is suitable to be fastened to the base and has a pair of slide tracks. The movable element has a pair of slide edges, a pair of slide hooks, and a turn portion. The slide hooks lock the slide tracks respectively, and the slide edges are supported by the slide tracks respectively. Therefore, the movable element substantially slides around a light axis of the zoom lens relative to the fixed element, so as to move the turn portion to turn the zoom bar. | 10-01-2009 |
20100045946 | Projection Apparatus - A projection apparatus includes a housing, a switch unit, a projection module, a circuit unit and a remote controller. The housing has an accommodation space and a containing groove. The switch unit is arranged in the containing groove. The projection module and the circuit unit are arranged in the accommodation space, and the circuit unit is electrically connected to the projection module and the switch unit. The remote controller is adapted to be contained in the containing groove and be taken out from the containing groove. When the remote controller is contained in the containing groove, the remote controller contacts the switch unit, and the circuit unit enables and disables the projection module according to a contact relation between the remote controller and the switch unit. The remote controller of the projection apparatus is easy to be contained. | 02-25-2010 |
20110109885 | PROJECTOR AND LENS COLLAR MODULE THEREOF - A projector includes a casing, a light source disposed in the casing and capable of providing an illumination beam, a light valve disposed in the casing and capable of converting the illumination beam into an image beam, a lens disposed in the casing and adapted to project the image beam, and the lens collar module. The lens collar module includes a fitting part and a lens collar. The fitting part is formed on the casing, and has a fitting opening and a first bump. The lens collar has a fitting periphery and a second bump. The fitting periphery is fitted to the fitting opening, the lens collar is adapted to be rotated and translated relative to the casing along an axial direction. Engagement of the first bump and the second bump limits rotation and translation of the lens collar relative to the casing along the axial direction. | 05-12-2011 |
20130027677 | PROJECTION APPARATUS WITH LOCKING STRUCTURE - A projection apparatus with locking structure includes an apparatus case including a main casing, a lid and at least one locking structure at the main casing and the lid, a light source, a light valve and a lens. The structure includes a slot having two opposite ends at the casing, at-least one elastic arm in the slot and at-least one positioning pillar at the lid. | 01-31-2013 |
Chin Tsung Chen, Hsin-Chu TW
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20100247742 | Three-dimensional object forming apparatus and method for forming three-dimensional object - A three-dimensional object forming apparatus is provided, which at least comprises: a construction stage, a printing module, plural temporary storage tanks, plural powder supplying tanks, a construction tank, a printing quality inspection component for forming a pattern to determine whether the printing module is blocked or not, a maintenance device, and a dust-proof device. | 09-30-2010 |
20110316907 | INKJET PRINTING SYSTEM - An inkjet printing system comprises: a liquid supply tank; a print device with at least one print cartridge, wherein there is an altitude difference between the print cartridge and the liquid supply tank; an internal pressure-adjusting device connecting to the liquid supply tank and the print cartridge; and working software for calculating a preliminary altitude, and a predetermined liquid supplementing altitude of the print cartridge. When a liquid level of a liquid inside the print cartridge is lower than the preliminary altitude and below an lower limit of the predetermined liquid supplementing altitude, the working software controls the internal pressure-adjusting device to suck partial gas from the print cartridge into the liquid supply tank to increase a negative pressure inside the print cartridge, and the liquid stored in the liquid supply tank is introduced into the print cartridge to balance the negative pressure inside the print cartridge. | 12-29-2011 |
Chiu Chun Chen, Hsin-Chu TW
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20100232178 | Light Guide Plate Assembly - Alight guide plate assembly for a backlight module is provided. The light guide plate assembly includes a plurality of light guide plates. Each light guide plate has a top face, at least one side face, and at least one connecting part. The connecting part is formed on the side face of the light guide plate. The connecting part has a connecting face, wherein the adjacent connecting faces are connected to each other. The top faces of the plurality of light guide plates are coplanar. A distance between the connecting face and the top face is ⅓ to 1/20 of the thickness of the light guide plate. | 09-16-2010 |
Cho-Yan Chen, Hsin-Chu TW
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20110141420 | MULTI-DOMAIN VERTICAL ALIGNMENT LIQUID CRYSTAL DISPLAY DEVICE AND PIXEL STRUCTURE THEREOF - An MVA LCD device includes a first alignment region, a second alignment region, a third alignment region, and a fourth alignment region. The liquid crystal molecules disposed in the first alignment region have a first aligning direction, and the azimuth angle of the first aligning direction is substantially between 70 and 110 degrees. The liquid crystal molecules disposed in the second alignment region have a second aligning direction, and the azimuth angle of the second aligning direction is substantially between 160 and 200 degrees. The liquid crystal molecules disposed in the third alignment region have a third aligning direction, and the azimuth angle of the third aligning direction is substantially between 250 and 290 degrees. The liquid crystal molecules disposed in the fourth alignment region have a fourth aligning direction, and the azimuth angle of the fourth aligning direction is substantially between −20 and 20 degrees. | 06-16-2011 |
20120113081 | DRIVING METHOD FOR BISTABLE DISPLAY - A driving method for a bistable display device includes setting a first duration and a second duration according to a frame period; applying a first voltage to a light valve layer in the first duration according to display data, so as to transform the light valve layer from a first state to a second state; and applying a second voltage in the second duration to the light valve layer in the second duration for the light valve layer to transform to the first state. Since the light valve layer of the bistable display device is already at the first state prior to displaying the next image, the light valve layer is not required to reset when switching displayed images, hence reducing the total number of frames required to display each image. | 05-10-2012 |
20130106922 | Transparent Display Device and Display Method Thereof | 05-02-2013 |
20140146032 | DRIVING CIRCUIT - A driving circuit electrically coupled between a first data line and a second data line and between a first scan line and a second scan line. The driving circuit includes a first switch, a second switch, a third switch, a fourth switch, a first sub-capacitor, a second sub-capacitor, a fifth switch, a sixth switch, a first voltage dividing unit and a second voltage dividing unit. The first voltage dividing unit is coupled between a second end of the fifth switch and a reference voltage end. The second voltage dividing unit is coupled between a second end of the sixth switch and the reference voltage end, for redistributing stored electric charges. | 05-29-2014 |
20140160103 | PIXEL DRIVING CIRCUIT, DRIVING METHOD THEREOF, AND PIXEL MATRIX - A pixel driving circuit is electrically coupled between a first data line and a second data line and between a first scan line and a second scan line, and includes a first switch, a second switch, a third switch, a fourth switch, a liquid crystal capacitor electrically connected between the first switch and the second switch, a first capacitor electrically connected to the first switch, a second capacitor electrically connected to the second switch, a first storage capacitor, a second storage capacitor and at least one switching unit. The first storage capacitor is electrically connected to the third switch and supplied by a reference voltage. The second storage capacitor is electrically connected to the fourth switch and supplied by the reference voltage. The at least one switching unit is used for redistributing charges in the pixel driving circuit. | 06-12-2014 |
Chu-Fu Chen, Hsin-Chu TW
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20090172617 | Advisory System for Verifying Sensitive Circuits in Chip-Design - A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits. | 07-02-2009 |
Chun-Hsiun Chen, Hsin-Chu TW
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20100013001 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY AND STRUCTURE THEREOF - A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer. | 01-21-2010 |
20100321341 | PHOTO SENSOR, METHOD OF FORMING THE SAME, AND OPTICAL TOUCH DEVICE - The present invention provides a photo sensor, a method of forming the photo sensor, and a related optical touch device. The photo sensor includes a first electrode, a second electrode, a first silicon-rich dielectric layer and a second silicon-rich dielectric layer. The first silicon-rich dielectric layer is disposed between the first electrode and the second electrode for sensing infrared rays, and the second silicon-rich dielectric layer is disposed between the first silicon-rich dielectric layer and the second electrode for sensing visible light beams. The multi-layer structure including the first silicon-rich dielectric layer and the second silicon-rich dielectric layer enables the single photo sensor to effectively detect both infrared rays and visible light beams. Moreover, the single photo sensor is easily integrated into an optical touch device to form optical touch panel integrated on glass. | 12-23-2010 |
20100327289 | FLAT DISPLAY PANEL, UV SENSOR AND FABRICATION METHOD THEREOF - A UV sensor comprises a silicon-rich dielectric layer with a refractive index in a range of about 1.7 to about 2.5 for serving as the light sensing material of the UV sensor. The fabrication method of the UV sensor can be integrated with the fabrication process of semiconductor devices or flat display panels. | 12-30-2010 |
20110037729 | OLED TOUCH PANEL AND METHOD OF FORMING THE SAME - A displaying region and a sensing region are defined in each pixel region of the OLED touch panel of the present invention. The readout thin film transistor of the sensing region is formed by the same processes with the drive thin film transistor of the displaying region. The top and bottom electrodes of the optical sensor are formed by the same processes with the top and bottom electrodes of the OLED. Accordingly, the present invention can just add a step of forming the patterned sensing dielectric layer to the processes of forming an OLED panel to integrate the optical sensor into the pixel region of the OLED panel. Thus, an OLED touch panel is formed. | 02-17-2011 |
20110141086 | ELECTROPHORETIC DISPLAY AND METHOD OF DRIVING THE SAME - An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage. | 06-16-2011 |
20150062088 | OPTICAL TOUCH DEVICE AND METHOD OF FORMING PHOTO SENSOR - A method of forming a photo sensor includes the following steps. A substrate is provided, and a first electrode is formed on the substrate. A first silicon-rich dielectric layer is formed on the first electrode for sensing an infrared ray, wherein the first silicon-rich dielectric layer comprises a silicon-rich oxide layer, a silicon-rich nitride layer, or a silicon-rich oxynitride layer. A second silicon-rich dielectric layer is formed on the first silicon-rich dielectric layer for sensing visible light beams, wherein the second silicon-rich dielectric layer comprises a silicon-rich oxide layer, a silicon-rich nitride layer, or a silicon-rich oxynitride layer. A second electrode is formed on the second silicon-rich dielectric layer. | 03-05-2015 |
Chun-Teh Chen, Hsin-Chu TW
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20100052742 | LIMIT SIGNAL GENERATOR, PWM CONTROL CIRCUIT, AND PWM CONTROL METHOD THEREOF - A PWM control circuit is disclosed. An oscillator generates a triangular signal, received by a limit signal generator to produce a limit signal accordingly. Corresponding to a rising period of the triangular signal, the limit signal sequentially experiences a first holding period, a rising period and a second holding period, wherein the limit signal has a first predetermined value during the first holding period and a second predetermined value during the second holding period. A compare/control circuit compares the limit signal with a detection signal corresponding to a current through a power switch, and controls the power switch accordingly. | 03-04-2010 |
20100124084 | POWER CONVERTER WITH CONTROL CIRCUIT AND RELATED CONTROL METHOD - A control circuit for use in a power converter has a multi-function terminal, a current comparator circuit, and an under-voltage detection circuit. The current comparator circuit compares current flowing through a power switch of the power converter with a reference value through the multi-function terminal when the power switch is on, and turns the power switch off when the current reaches the reference value. The under-voltage detection circuit determines whether an input voltage of the power converter is less than a predetermined value through the multi-function terminal when the power switch is turned off. | 05-20-2010 |
20110057520 | Power Management Integrated Circuit and Power Management Method - The power management integrated circuit has a startup circuit, a switch controller and a standby controller. Powered by a power source, the startup circuit provides electric power to an operational power source during a startup period. The switch controller controls a power switch to store or release energy in an energy conversion unit. Powered by the power source, the standby controller receives a standby signal. When the standby signal is asserted, the standby controller disables the startup circuit and the switch controller, thereby startup circuit not providing electric power to the operational power source and the switch controller continuously turning off the power switch. | 03-10-2011 |
20110068768 | SWITCHING POWER SUPPLY AND RELATED CONTROL METHOD - A switching power supply includes a power switch, an adjusting circuit and a limit signal generator. The power switch operates according to a switch control signal. The adjusting circuit adjusts the turn-on time of the switch control signal according to a limit signal and a detecting signal which corresponds to the current passing the power switch. When the detecting signal exceeds or is equal to the limit signal, the limit signal generator samples a reference signal and updates the limit signal according to the sampled reference signal. | 03-24-2011 |
20120112564 | Discharging module applied in a switched-mode power supply and method thereof - A discharging module applied in a switched-mode power supply includes a detecting circuit and a discharging circuit. The detecting circuit is coupled to an input port of the switched-mode power supply. The detecting circuit determines if the input port is supplied power according to an AC input power of the switched-mode power supply. When the detecting circuit determines that the input port is not supplied power, the detecting circuit controls the discharging circuit to provide a discharging path for discharging the input port. In this way, the switched-mode power supply does not require a discharging resistor for discharging the input port. Hence, the power consumed when the switched-mode power supply is unloaded is reduced. | 05-10-2012 |
Dian-Hau Chen, Hsin-Chu TW
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20100308444 | Method of Manufacturing an Electronic Device - In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers. | 12-09-2010 |
20120313256 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 12-13-2012 |
20130260563 | Mask Treatment for Double Patterning Design - A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask. | 10-03-2013 |
20140001638 | Semiconductor Devices and Methods of Manufacture Thereof | 01-02-2014 |
Fei-Yuh Chen, Hsin-Chu TW
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20100140687 | High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region. | 06-10-2010 |
20110163375 | High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region. | 07-07-2011 |
Fu-Chuan Chen, Hsin-Chu TW
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20110110122 | FLYBACK CONVERTER SYSTEM CAPABLE OF PREVENTING TWO SIDE SWITCHES FROM BEING TURNED ON SIMUTANEOUSLY - A flyback converter system prevents a primary side switch and a secondary side switch from being turned on simultaneously through a controller. The controller includes a turning on switch module, a turning off switch module, and an enabling switch module. The turning on switch module is for turning on the secondary side switch. The turning off switch module switches off the secondary side switch according to the impedance of a load and the switch cycle of the secondary side switch. The enabling switch module enables the secondary side switch according to the impedance of the load. | 05-12-2011 |
Fu-Tung Chen, Hsin-Chu TW
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20090243500 | LCD and Backlight Module Thereof - A backlight module includes fluorescent lamps, an inverter for supplying power for the lamps, dimming circuits each connecting the lamp in series, a signal processor for converting a video signal into a dimming signal, and a control unit. The lamps are disposed as an array having more than two columns and two rows on a substrate. The control unit electrically connects the signal processor and the dimming circuit and changes the luminance of the lamps by adjusting the dimming circuit according to the dimming signal. | 10-01-2009 |
Hai-Ching Chen, Hsin-Chu TW
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20110006428 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 01-13-2011 |
20110223762 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 09-15-2011 |
20120282768 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 11-08-2012 |
20120289062 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 11-15-2012 |
20130249097 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 09-26-2013 |
20140084421 | Adhesion Promoter Apparatus and Method - A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first adhesion promoter layer formed over the reflecting layer, a bottom cladding layer deposited over the first adhesion promoter layer, a core layer formed over the bottom cladding layer and a top cladding layer formed over the core layer. | 03-27-2014 |
20140167229 | PROTECTING LAYER IN A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer. | 06-19-2014 |
20140206110 | Etchant and Etching Process - A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system. | 07-24-2014 |
20140206191 | Etchant and Etching Process - A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide. | 07-24-2014 |
20140231999 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 08-21-2014 |
20140252619 | INTERCONNECT STRUCTURE THAT AVOIDS INSULATING LAYER DAMAGE AND METHODS OF MAKING THE SAME - A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer. | 09-11-2014 |
20140252624 | Semiconductor Devices and Methods of Forming Same - A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration. | 09-11-2014 |
20140269804 | Package Structure and Methods of Forming Same - A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. | 09-18-2014 |
20140269805 | Light Coupling Device and Methods of Forming Same - An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index. | 09-18-2014 |
20140363121 | Integrated Metal Grating - An integrated circuit includes a substrate, a metal grating disposed over the substrate, and a waveguide layer disposed over or under the metal grating. The metal grating is arranged to change a propagation direction of an optical signal and the waveguide layer is arranged to guide the optical signal to a desired direction. | 12-11-2014 |
Ho-Hsiang Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20100164069 | Reducing High-Frequency Signal Loss in Substrates - An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region. | 07-01-2010 |
20100264509 | Enhanced Transmission Lines for Radio Frequency Applications - An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first portion directly over the deep well region and a second portion directly under the deep well region. A transmission line is directly over the depletion region. | 10-21-2010 |
20120104575 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 05-03-2012 |
20120133446 | Quadrature Voltage Controlled Oscillator Including Transmission Line - A circuit includes an oscillator circuit including a first oscillator and a second oscillator. The first and the second oscillators are configured to generate signal having a same frequency and different phases. A transmission line is coupled between the first and the second oscillators. | 05-31-2012 |
20120161285 | Reducing High-Frequency Signal Loss in Substrates - An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region. | 06-28-2012 |
20120268229 | Compact Vertical Inductors Extending in Vertical Planes - A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor. | 10-25-2012 |
20130277794 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 10-24-2013 |
20140264628 | Multi-Gate and Complementary Varactors in FinFET Process - A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor. | 09-18-2014 |
Hong-Ming Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20090237945 | Backlight Module with Integrated Base and Method of Manufacturing Thereof - A backlight module, a base used therein, and a manufacturing method thereof are provided. The backlight module includes a base and a slice-shaped circuit. The base has a back plate including a plate portion and a mezzanine portion. The mezzanine portion is parallelly offset from the plate portion, and the initial position of the mezzanine portion becomes an opening on the plate portion. Because the mezzanine portion is parallelly offset from the plate portion, a containing space is formed between an inner side of the mezzanine portion and the plane of the plate portion. A side of the mezzanine portion and a side of the plate portion corresponding to the opening together form a first slit. The slice-shaped circuit is inserted into the containing space through the first slit and stays between the plate portion and the mezzanine portion. | 09-24-2009 |
Hsin-Li Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20090027371 | PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME - A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer. | 01-29-2009 |
20110316830 | PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME - A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer. | 12-29-2011 |
20140051200 | METHOD FOR FABRICATING PHOTO DETECTOR - A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region. The first electrodes are electrically connected to the first patterned semiconductor layer. | 02-20-2014 |
Hua-Shing Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20090066918 | PROJECTOR - A projector includes a case, a separating plate, an electronic component system, a light source device and a blocking device. The case has a space defined therein. The separating plate is arranged in the case to divide the space into a first space and a second space. The electronic component system is arranged in the first space. The light source device for emitting light is arranged in the second space. The blocking device has a blocking plate which is arranged adjacent to the separating plate and controlled to be located from a first position and a second position. When the blocking plate is located at the first position, air flows from the first space into the second space. When the blocking plate is located at the second position, air in the second space is prevented from entering into the first space. | 03-12-2009 |
I-Fang Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20100134463 | Driving Method of Display Panel with Half-Source-Driving Structure - An exemplary driving method of a display panel with half-source-driving structure is provided. The display panel includes at least one pixel each using a capacitor to store a voltage. A terminal of the capacitor is adapted to receive a display data inputted from a data line, and another terminal of the capacitor is electrically coupled to a common electrode. The driving method includes: obtaining a direct current power signal; coupling an alternating current signal with the direct current power signal to generate a common electrode driving signal; and applying the common electrode driving signal to the common electrode. A rising time of a rising edge and a falling time of a falling edge of the common electrode driving signal are modified to improve a V-line mura phenomenon of the display panel. | 06-03-2010 |
20130155035 | METHOD FOR DRIVING PIXEL CIRCUITS - A method for driving a pixel circuit, which is adapted to drive a first pixel circuit coupled to a first gate line and a second pixel circuit coupled to a second gate line, is disclosed. The first pixel circuit receives display data before the second pixel circuit does. The method provides only one first enable pulse to the first gate line in a frame, and provides a second enable pulse and a third enable pulse to the second gate line in the same frame. The starting time of the second enable pulse is in an enabled time period of the first enable pulse, and the enabled time period of the third enable pulse is after the enabled time periods of the first and second enable pulses. | 06-20-2013 |
20140132651 | DISPLAY AND METHOD OF GENERATING AN IMAGE WITH UNIFORM BRIGHTNESS - A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line. | 05-15-2014 |
Jeng-Horng Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20090268184 | System and Method for Direct Writing to a Wafer - A direct-write (DW) exposure system is provided which includes a stage for holding a substrate and configured to scan the substrate along an axis during exposure, a data processing module for processing pattering data and generating instructions associated with the patterning data, and an exposure module that includes a plurality of beams that are focused onto the substrate such that the beams cover a width that is larger than a width of a field size and a beam controller that controls the plurality of beams in accordance with the instructions as the substrate is scanned along the axis. The widths are in a direction different from the axis. | 10-29-2009 |
20110226970 | SYSTEM AND METHOD FOR GENERATING DIRECT-WRITE PATTERN - A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam. | 09-22-2011 |
20110244378 | DEVICE AND METHOD FOR PROVIDING WAVELENGTH REDUCTION WITH A PHOTOMASK - Disclosed is a photomask having a wavelength-reducing material that may be used during photolithographic processing. In one example, the photomask includes a transparent substrate, an absorption layer having at least one opening, and a layer of wavelength-reducing material (WRM) placed into the opening. The thickness of the WRM may range from approximately a thickness of the absorption layer to approximately ten times the wavelength of light used during the photolithographic processing. In another example, the photomask includes at least one antireflection coating (ARC) layer. | 10-06-2011 |
20120192126 | SYSTEMS AND METHODS PROVIDING ELECTRON BEAM PROXIMITY EFFECT CORRECTION - A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium. | 07-26-2012 |
20120237877 | ELECTRON BEAM DATA STORAGE SYSTEM AND METHOD FOR HIGH VOLUME MANUFACTURING - The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table. | 09-20-2012 |
20130055173 | GEOMETRIC PATTERN DATA QUALITY VERIFICATION FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying. | 02-28-2013 |
20130061187 | STRIPING METHODOLOGY FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system. | 03-07-2013 |
20130293899 | APPARATUS FOR CHARGED PARTICLE LITHOGRAPHY SYSTEM - The present disclosure describes an apparatus of leveling a substrate in a charged particle lithography system. In an example, the apparatus includes a cantilever-based sensor that includes an optical sensor and a cantilever structure. The optical sensor determines a distance between the optical sensor and a surface of the substrate based on light reflected from the cantilever structure. In an example, a first distance is between the cantilever structure and optical sensor, a second distance is a height of the cantilever structure, and a third distance is between the optical sensor and the surface of the substrate. The optical sensor determines the first distance based on the light reflected from the cantilever structure, such that the third distance is determined from the first distance and the second distance. | 11-07-2013 |
20130316289 | Electron Beam Data Storage System and Method for High Volume Manufacturing - The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table. | 11-28-2013 |
20130320243 | EFFICIENT SCAN FOR E-BEAM LITHOGRAPHY - The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning. | 12-05-2013 |
20130323648 | SMART SUBFIELD METHOD FOR E-BEAM LITHOGRAPHY - The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved. | 12-05-2013 |
20140023972 | Data Process for E-Beam Lithography - The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system. | 01-23-2014 |
20140033144 | PROVIDING ELECRON BEAM PROXIMITY EFFECT CORRECTION BY SIMULATING WRITE OPERATIONS OF POLYGONAL SHAPES - A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium. | 01-30-2014 |
20140038107 | Method and System for E-Beam Lithography with Multi-Exposure - The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer. | 02-06-2014 |
20140099582 | Smart Subfield Method For E-Beam Lithographny - The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved. | 04-10-2014 |
20140111781 | METHOD AND APPARATUS FOR ULTRAVIOLET (UV) PATTERNING WITH REDUCED OUTGASSING - A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus. | 04-24-2014 |
20140268074 | Lithography System with an Embedded Cleaning Module - The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism. | 09-18-2014 |
20140268086 | Extreme Ultraviolet Lithography Process and Mask - The present disclosure is directed towards lithography processes. In one embodiment, a patterned mask is provided. An information of a position of diffraction light (PDL) on a pupil plane of a projection optics box (POB) is used to define as a light-transmitting region of a pupil filter. The patterned mask is exposed by an on-axis illumination (ONI) with partial coherence σ less than 0.3. The pupil filter is used to transmit diffraction light to a target. | 09-18-2014 |
20140268091 | Extreme Ultraviolet Lithography Process and Mask - A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. The system and process includes receiving a mask with two states, which have 180 degree phase difference to each other. These different states are assigned to adjacent main polygons and adjacent assist polygons of the mask. A nearly on-axis illumination (ONI) with partial coherence σ less than 0.3 is utilized to expose the mask to produce diffracted lights and non-diffracted lights. A majority portion of the non-diffracted lights and diffracted light with diffraction order higher than 1 are removed. Diffracted light having +1-st and −1-st diffracted order are collected and directed by a projection optics box (POB) to expose a target. | 09-18-2014 |
20140268092 | Extreme Ultraviolet Lithography Process and Mask - A process of an extreme ultraviolet lithography (EUVL) is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask with multiple states. These different states of the EUV mask are assigned to adjacent polygons and adjacent assist polygons. The EUV mask is exposed by a nearly on-axis illumination (ONI) with partial coherence σ less than 0.3 to produce diffracted lights and non-diffracted lights. Most of the non-diffracted lights reflected from main polygons and reflected lights from assist polygons are removed. The diffracted lights and the not removed non-diffracted lights reflected from main polygons are collected and directed to expose a target by a projection optics box. | 09-18-2014 |
20140272678 | Structure and Method for Reflective-Type Mask - The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer formed on the substrate; a capping layer formed on the reflective multilayer and having a hardness greater than about 8; and an absorber layer formed on the capping layer and patterned according to an integrated circuit layout. | 09-18-2014 |
20140272679 | Extreme Ultraviolet Lithography Process and Mask - An extreme ultraviolet lithography (EUVL) process is disclosed. The process comprises receiving a mask. The mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML) over one surface of the LTEM substrate, a first region having a phase-shifting layer over the reflective ML, and a second region having no phase-shifting layer over the reflective ML. The EUVL process also comprises exposing the mask by a nearly on-axis illumination with partial coherence less than 0.3 to produce diffracted light and non-diffracted light, removing at least a portion of the non-diffracted light, and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target. | 09-18-2014 |
20140272680 | Method For Mask Fabrication And Repair - A method for repairing a phase-defect region in a patterned mask for extreme ultraviolet lithography (EUVL) is disclosed. A patterned mask for EUVL is received. The patterned mask includes an absorptive region having an absorption layer over a defect-repairing-enhancement (DRE) layer, a reflective region having the DRE layer without the absorption layer on top of it, a defect and a phase-defect region resulting from the defect and intruding the reflective region. A location and a shape of the phase-defect region is determined. A portion or portions of the DRE layer in the reflective region is removed according to the location and the shape of the phase-defect region to compensate the effect of the phase-defect region. | 09-18-2014 |
20140272682 | Extreme Ultraviolet Lithography Process and Mask - The present disclosure is directed towards an extreme ultraviolet (EUV) mask. The EUV mask includes a low thermal expansion material (LTEM) substrate. The EUV mask has a first region and a second region. The EUV mask also includes a structure disposed in the first region. The structure has a multiple facets with an angle to each other. The EUV mask also includes a conformal reflective multilayer (ML) disposed over the structure in the first region and over the LTEM substrate in the second region. The conformal reflective ML has a similar surface profile as the structure in the first region and a flat surface profile in the second region. | 09-18-2014 |
20140272686 | Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same - A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate and a patterned absorption layer disposed over the reflective multilayer. The patterned absorption layer has a mask image region and a mask border region. The exemplary mask also includes a mask border frame disposed over the mask border region. The mask border frame has a top surface and a bottom surface. The top surface is not parallel to the bottom surface. | 09-18-2014 |
20140272721 | Extreme Ultraviolet Lithography Process and Mask - An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose. | 09-18-2014 |
20140342272 | Method to Define Multiple Layer Patterns With a Single Exposure by E-Beam Lithography - The present disclosure provides a method that includes forming a first resist layer on a substrate; forming a second resist layer over the first resist layer; and performing an electron-beam (e-beam) lithography exposure process to the first resist layer and the second resist layer, thereby forming a first latent feature in the first resist layer and a second latent feature in the second resist layer. | 11-20-2014 |
20140342564 | Photomask With Three States For Forming Multiple Layer Patterns With A Single Exposure - The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern. | 11-20-2014 |
20140347644 | SYSTEM AND METHOD FOR PERFORMING LITHOGRAPHY PROCESS IN SEMICONDUCTOR DEVICE FABRICATION - Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height. | 11-27-2014 |
20140367588 | Method and System for E-Beam Lithography with Multi-Exposure - The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer. | 12-18-2014 |
20150024305 | EXTREME ULTRAVIOLET LIGHT (EUV) PHOTOMASKS AND FABRICATION METHODS THEREOF - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer. | 01-22-2015 |
20150037712 | Extreme Ultraviolet (EUV) Mask, Method Of Fabricating The EUV Mask And Method Of Inspecting The EUV Mask - An out-of-band (OoB) suppression layer is applied on a reflective multiplayer (ML) coating, so as to avoid the OoB reflection and to enhance the optical contrast at 13.5 nm A material having a low reflectivity at wavelength of 193-257 nm, for example, silicon carbide (SiC), is used as the OoB suppression layer. A method of fabricating an EUV mask having the OoB suppression layer and a method of inspecting an EUV mask having the OoB suppression are also provided. | 02-05-2015 |
20150064611 | Extreme Ultraviolet (Euv) Mask And Method Of Fabricating The Euv Mask - A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance. | 03-05-2015 |
20150069622 | Via Definition Scheme - A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer. | 03-12-2015 |
20150072271 | Extreme Ultraviolet Lithography Process and Mask - A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. An EUVL process includes receiving a mask pair having a same pattern. The mask pair includes an extreme ultraviolet (EUV) mask and a low EUV reflectivity mask. A first exposure process is performed by using the EUV mask to expose a substrate. A second exposure process is performed by using the low EUV reflectivity mask to expose the same substrate. The first exposure process is conducted according to a first exposure dose matrix and the second exposure process is conducted according to a second exposure dose matrix. | 03-12-2015 |
20150072519 | Metal and Via Definition Scheme - A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer. | 03-12-2015 |
20150085264 | ROTARY EUV COLLECTOR - An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force. | 03-26-2015 |
20150085268 | Extreme Ultraviolet Lithography Process And Mask - A system of an extreme ultraviolet lithography (EUVL) is disclosed. an extreme ultraviolet lithography (EUVL) system includes an extreme ultraviolet (EUV) reflection-type mask having a patterned flare-suppressing-by-phase-shifting (FSbPhS) layer disposed over a patterned absorption layer. The system also includes a radiation to expose the EUV mask and a projection optics box (POB) to collect and direct the radiation that reflects from the EUV mask to expose a target. | 03-26-2015 |
Jenq-Shyong Chen, Hsin-Chu TW
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20090168604 | DUAL-RECEIVING ULTRASONIC DISTANCE MEASURING EQUIPMENT - A dual-receiving ultrasonic distance measuring equipment is disclosed, which uses a transmitter and two receivers, one of which serves as an objective and the other as a reference, to perform distance measurement. The transmitter and the reference receiver are fixedly installed on a phase adjusting platform, capable of adjusting a reference phase by fine-tuning the distance between the transmitter and the reference receiver. As the objective receiver is disposed on an object under measurement which is a distance away from the phase adjusting platform, there will be a phase shift due to the propagation of an ultrasonic wave from the transmitter as it is received by the two receivers. And thereby, the distance between the two receivers can be calculated based on the phase shift. The aforesaid ultrasonic distance measuring equipment can be applied in the positioning system of high precision machinery or other non-contact distance measuring system. | 07-02-2009 |
Jyh-An Chen, Hsin-Chu TW
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20100154878 | Electrode Structure and Fabrication of the Dye-Sensitized Solar Cell - The electrode according to the invention comprises a substrate, an indium tin oxide film and a semiconductor layer and is produced under a processing condition that the substrate is subjected to ITO sputtering in a sputter chamber at a temperature of less than 200° C., preferably without being treated with heat, and then undergoes a high temperature treatment so as to form a stable ITO film. By this way, a semiconductor layer could be also formed on the indium tin oxide film. The electrode structure so produced is resistant to high temperature and has a reduced resistance change ratio. The electrode structure is especially suited for being used in a dye-sensitized solar cell to enhance the photoelectric conversion efficiency thereof. | 06-24-2010 |
20110001721 | Digital Capacitive Touch Panel Structure - The present invention discloses a touch panel structure formed by an anti-scratch surface layer and a capacitive sensor layer, and a transparent lamination layer is used for pasting the two into a panel. The capacitive sensor layer includes an X-axis first transparent conductive layer and a Y-axis second transparent conductive layer formed on both sides of a transparent plastic carrier to provide a touch panel structure having the advantages of a relatively low material cost, a light weight, an easy manufacturing and molding, a better lamination yield and a flexible and break-free feature. | 01-06-2011 |
Ker-Min Chen, Hsin-Chu TW
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20100164583 | Method and System for Setup/Hold Characterization in Sequential Cells - An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell. | 07-01-2010 |
20100190299 | Semiconductor Device with Two or More Bond Pad Connections for Each Input/Output Cell and Method of Manufacture Thereof - A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component. | 07-29-2010 |
20110055778 | Automatic Application-Rule Checker - A method of checking an integrated circuit design database includes providing the integrated circuit design stored in a storage media; providing application rules; and providing an instance abstract of instances of libraries and IP(s). Instance-level information is extracted from the integrated circuit design database. An application-rule check is performed against the instance-level information using the information provided in an abstract file. | 03-03-2011 |
Keui Shun Chen, Hsin-Chu TW
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20090081591 | METHOD FOR PATTERNING A PHOTOSENSITIVE LAYER - The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask. | 03-26-2009 |
20120114872 | METHOD FOR PATTERNING A PHOTOSENSITIVE LAYER - The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask. | 05-10-2012 |
Ke-Wei Chen, Hsin-Chu TW
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20100263945 | Rechargeable Electromagnetic Pen - A rechargeable electromagnetic pen is disclosed. The rechargeable electromagnetic pen comprises a rechargeable and storable electrical power source system, an electrical power receiving terminal and a signal transformation circuit. The electrical power source system provides the rechargeable electromagnetic pen with electrical power for emitting electromagnetic signal to an array of antenna loops of a digital tablet. The electrical power-receiving terminal receives electrical power signal generating from electric energy transformation and transmission between the electrical power receiving terminal and a charge site. The signal transformation circuit processes and transforms the electrical power signal and charges the electrical power source system. | 10-21-2010 |
20100271300 | Multi-Touch Pad Control Method - A multi-touch pad control method is disclosed. The method comprises the following steps. First of all, a primary cursor is detected. Then a first touch motion is detected, if there is no first touch motion, primary cursor is re-detected. Next a secondary cursor is detected if there is a first touch motion. Then a second touch motion is detected. A first function is performed if there is no second touch motion. A first direction of the second touch motion is detected, if the second touch motion controlling the secondary cursor is detected. A second function is performed if the second touch motion is toward first direction. A second direction of the second touch motion is detected, if the second touch motion is not toward the first direction. A third function is performed if the second touch motion is toward the second direction, wherein the first function is performed if the second touch motion controlling the secondary cursor is detected and the second touch motion is neither toward the first direction nor the second direction. | 10-28-2010 |
20110227588 | LAYOUT FOR ANTENNA LOOPS HAVING BOTH FUNCTIONS OF CAPACITANCE INDUCTION AND ELECTROMAGNETIC INDUCTION - The present invention relates to a layout for antenna loops having both functions of capacitance induction and electromagnetic induction, and particularly relates to the layout for antenna loops having both functions of capacitance induction and electromagnetic induction, wherein the capacitance detection elements are integrated with the antenna loops. In this layout for antenna loops, each of the antenna loops therein is separated into three sections, and there are several geometric structures fabricated in two of these sections. These geometric structures are capacitance detection elements. Therefore, the two sections are directly fabricated to be the capacitance detection elements because of these geometric structures. By this way, the antenna loops can be integrated with the capacitance detection elements and the capacitance detection elements do not prevent the antenna loops from receiving the electromagnetic signals. | 09-22-2011 |
Kuo-Yin Chen, Hsin-Chu TW
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20100174933 | System and Method for Reducing Processor Power Consumption - A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module. | 07-08-2010 |
Li-Kai Chen, Hsin-Chu TW
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20110147733 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode. The passivation layer has a groove formed therein, and the groove surrounds the oxide semiconductor layer. | 06-23-2011 |
Maw-Song Chen, Hsin-Chu TW
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20090174833 | PIXEL STRUCTURE AND METHOD OF MAKING THE SAME - A pixel structure includes a substrate, a floating light-shielding pattern disposed on the substrate, an insulating layer disposed on the substrate and the light-shielding pattern, a data line disposed over and corresponding to the light-shielding pattern, a dielectric layer disposed on the data line and the insulating layer, and a third layer conductive pattern disposed on the dielectric layer. The third layer conductive pattern includes a common line and a common pattern. The common pattern includes two common branches arranged in parallel, and there is a space between the two common branches and over the data line. | 07-09-2009 |
20100171687 | DISPLAY DEVICE HAVING SLIM BORDER-AREA ARCHITECTURE AND DRIVING METHOD THEREOF - A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines. | 07-08-2010 |
20100296016 | ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate includes a base, scan lines, data lines and gate tracking lines disposed on the base. Each of the gate tracking lines has first portions, auxiliary portions and junction portions, wherein the junction portion and the first portion are formed in different layers. One of the junction portions is electrically connected with corresponding one of the first portions. | 11-25-2010 |
Ming-Wen Chen, Hsin-Chu TW
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20090219492 | DETECTING DEVICE - A detection device is mounted in a projector for detecting relations between an object and the projector. The detection device includes a detecting switch, a connector and a detecting circuit. When the object is placed into the detecting switch, the detecting switch is in an off state. When the object is withdrawn from the detecting switch, the detecting switch is in an on state. The connector is electrically connected to the detecting switch. The detecting circuit is electrically connected to the connector for activating the projector to be operated in a first mode in response to the off state of the detecting switch and activating the projector to be operated in a second mode in response to the on state of the detecting switch. The first mode and the second mode are associated with the temperature inside the projector. | 09-03-2009 |
20130207891 | PROJECTION SYSTEM - A projection system includes a pointing sensing apparatus and a projection apparatus. The pointing sensing apparatus senses at least one of a plurality of instruction signals, and outputs a sensing signal accordingly. The projection apparatus displays a pointing pattern according to the sensing signal. The projection apparatus includes a control module, a first storage module and a second storage module coupled to the control module. The control module receives a plurality of image signals of different formats and generates a plurality of shrink-image data according to the image signals, respectively. The first storage module stores one of the image signals. The second storage module stores the shrink-image data. The projection apparatus displays a normal display image according to contents stored in the first storage module or displays a shrink array image according to contents stored in the second storage module in response to a selecting signal. | 08-15-2013 |
Pei-Ming Chen, Hsin-Chu TW
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20110141086 | ELECTROPHORETIC DISPLAY AND METHOD OF DRIVING THE SAME - An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage. | 06-16-2011 |
20130099238 | LIQUID CRYSTAL DISPLAY HAVING A HIGH APERTURE RATIO - A (liquid crystal display) LCD includes a pixel array and a gate driving circuit. The pixel array includes a plurality of first oxide thin film transistors, a first oxide thin film transistor of the first oxide thin film transistors with a shortest channel length having a first channel length. The gate driving circuit is coupled to the pixel array for driving the pixel array, and includes a plurality of second oxide thin film transistors. The second oxide thin film of the second oxide thin film transistors with a longest channel length has a second channel length. A ratio of the second channel length and the first channel length is greater than 1.5. By limiting the ratio of the second channel length and the first channel length, the aperture ratio of the display panel can be improved without deteriorating the operation stability of the LCD. | 04-25-2013 |
20140138714 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening. | 05-22-2014 |
20150048367 | ARRAY SUBSTRATE - An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening. | 02-19-2015 |
Ping-Lin Chen, Hsin-Chu TW
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20110057868 | LIQUID CRYSTAL DISPLAY CAPABLE OF SWITCHING COMMON VOLTAGE - A liquid crystal display capable of switching the common voltage includes a display panel and a printed circuit board. The display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels. Each pixel includes a transistor, a storage capacitor, and a liquid crystal capacitor. The first ends of the storage capacitor and the liquid crystal capacitor are electrically connected to the transistor. The second end of the liquid crystal capacitor is electrically connected to a common voltage source. The printed circuit board includes a switcher for switching the second end of the storage capacitor electrically connecting to common voltage source, an analog voltage source, or a ground. | 03-10-2011 |
20110317803 | SHIFT REGISTER CIRCUIT AND SHIFT REGISTER - An exemplary shift register circuit includes a plurality of shift registers for sequentially outputting a plurality of driving pulse signals. Among each M number of the shift registers for sequentially outputting M number of the driving pulse signals, the shift register for lastly outputting one of the M number of driving pulse signals is enabled, by (M−1) number of start pulse signals sequentially outputted from the remained (M−1) number of the shift registers, to generate the driving pulse signal. Herein, M is a positive integer greater than 2. Moreover, a circuit structure of a shift register also is provided. | 12-29-2011 |
Ren-Yi Chen, Hsin-Chu TW
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20100052742 | LIMIT SIGNAL GENERATOR, PWM CONTROL CIRCUIT, AND PWM CONTROL METHOD THEREOF - A PWM control circuit is disclosed. An oscillator generates a triangular signal, received by a limit signal generator to produce a limit signal accordingly. Corresponding to a rising period of the triangular signal, the limit signal sequentially experiences a first holding period, a rising period and a second holding period, wherein the limit signal has a first predetermined value during the first holding period and a second predetermined value during the second holding period. A compare/control circuit compares the limit signal with a detection signal corresponding to a current through a power switch, and controls the power switch accordingly. | 03-04-2010 |
20100124080 | CURRENT CONTROL METHOD AND APPARATUS - Current control method and apparatus are disclosed. A current limiter is coupled to a switch connected in series with an energy transfer element of a power supply. The current limiter detects a current flowing through the switch and, when the current exceeds a current limit signal, turns off the switch. A limit signal generator provides the current limit signal, detects the maximum current value of the current, and updates the current limit signal according to the maximum current value and an ideal current limit value. | 05-20-2010 |
20100124084 | POWER CONVERTER WITH CONTROL CIRCUIT AND RELATED CONTROL METHOD - A control circuit for use in a power converter has a multi-function terminal, a current comparator circuit, and an under-voltage detection circuit. The current comparator circuit compares current flowing through a power switch of the power converter with a reference value through the multi-function terminal when the power switch is on, and turns the power switch off when the current reaches the reference value. The under-voltage detection circuit determines whether an input voltage of the power converter is less than a predetermined value through the multi-function terminal when the power switch is turned off. | 05-20-2010 |
20110032024 | Integrated Circuit and Related Method for Determining Operation Modes - An integrated circuit and a related method for determining an operation mode are disclosed. The exemplified integrated circuit includes a controller, a multi-function pin, and a mode determination circuit. The controller controls a power switch and is being set to operate in one of the operation modes including a first operation mode and a second operation mode. The multi-function pin is connected to an external resistor. The mode determination circuit detects a signal from the multi-function pin. The signal represents the resistance of the external resistor. If the resistance is within a first range, the controller is operated in the first operation mode. If the resistance is within a second range, the controller is operated in the second operation mode. | 02-10-2011 |
20110068768 | SWITCHING POWER SUPPLY AND RELATED CONTROL METHOD - A switching power supply includes a power switch, an adjusting circuit and a limit signal generator. The power switch operates according to a switch control signal. The adjusting circuit adjusts the turn-on time of the switch control signal according to a limit signal and a detecting signal which corresponds to the current passing the power switch. When the detecting signal exceeds or is equal to the limit signal, the limit signal generator samples a reference signal and updates the limit signal according to the sampled reference signal. | 03-24-2011 |
20120008343 | High-Voltage Startup Method and Power Management Apparatus - A high-voltage device provides a constant current drained from a high voltage source to charge a filter capacitor, where a voltage level of the higher voltage source is higher than 90 volts. When the operation voltage of the filter capacitor exceeds a first predetermined value, the charging of the filter capacitor by the constant current is stopped. A feedback loop is then used to maintain the operating voltage at substantially a second predetermined value lower than the first one. | 01-12-2012 |
20120112564 | Discharging module applied in a switched-mode power supply and method thereof - A discharging module applied in a switched-mode power supply includes a detecting circuit and a discharging circuit. The detecting circuit is coupled to an input port of the switched-mode power supply. The detecting circuit determines if the input port is supplied power according to an AC input power of the switched-mode power supply. When the detecting circuit determines that the input port is not supplied power, the detecting circuit controls the discharging circuit to provide a discharging path for discharging the input port. In this way, the switched-mode power supply does not require a discharging resistor for discharging the input port. Hence, the power consumed when the switched-mode power supply is unloaded is reduced. | 05-10-2012 |
20120120533 | CONTROLLERS, POWER SUPPLIES AND CONTROL METHODS - Power supplies together with related over voltage protection methods and apparatuses. A power supply has a transformer including a primary winding and an auxiliary winding. A power switch is coupled to the primary winding and a sensing resistor coupled between the power switch and a grounding line. A multi-function terminal of a controller is coupled to the sensing resistor. A diode and a first resistor is coupled between the auxiliary winding and the multi-function terminal. | 05-17-2012 |
20120140370 | Protection Circuit and Protection Method - A controller is applied with a protection circuit and a protection method. A controller detects an input signal generated by a current flowing through a detection resistor, thereby turning on or off a switch, for controlling the current. A shielding time generator provides a shielding time. When the switch is turned on and when a current timing without the shielding time, a short-circuit detector compares the input signal with a first reference voltage, thereby asserting a short-circuit detection signal. When the switch is turned off or when the current timing is during the shielding time, the short-circuit detection signal is not asserted. Each time the short-circuit detection signal is asserted, a logic controller turns off the switch, thereby reducing the current. | 06-07-2012 |
20120300499 | CONTROL CIRCUIT OF A SWITCHED-MODE POWER CONVERTER AND METHOD THEREOF - A method for controlling voltage crossing a power switch of a switched-mode power converter is disclosed. The method comprises the steps of: controlling a switch frequency of a power switch of a switched-mode power converter to a first frequency as activating the switched-mode power converter; and changing the switch frequency of the power switch to a second frequency after a specific amount of time; wherein the first frequency is lower than the second frequency. | 11-29-2012 |
20130070486 | CONTROL METHODS AND CONTROLLERS - Control methods and controller thereof for a power supply including a power switch and an inductor. The power switch is turned on to increase the inductor current through the inductor, which is sensed to generate a current-sense signal. The current-sense signal is added up with an adjusting signal to generate a summation signal. The power switch is turned off if the summation signal is higher than a peak limit. The turn-on time of the power switch is detected to update the adjusting signal. | 03-21-2013 |
20130083562 | POWER SUPPLY, POWER MANAGEMENT DEVICE APPLIED TO A POWER SUPPLY, AND METHOD FOR PERFORMING BROWN-OUT PROTECTION AND OVERHEAT PROTECTION OF A POWER MANAGEMENT DEVICE - A power supply can provide brown-out protection and overheat protection. The power supply includes a rectifier, a transformer, and a power management device. The rectifier is used for receiving an alternating current voltage. The alternating current voltage has a voltage cycle. The transformer coupled to the rectifier has an inductor coupled to a switch for supplying an output voltage. The power management device is used for controlling the switch to make the inductor save power or release power. The power management device has a multi-functional pin coupled to the rectifier for receiving a detection voltage corresponding to a positive half cycle of the alternating current voltage. The multi-functional pin is also coupled to a thermistor for receiving an overheat protection signal. | 04-04-2013 |
20130301302 | POWER SUPPLY AND POWER CONTROLLER - Power supplies and power controllers are disclosed. A disclosed power supply has a power controller, a power switch, an auxiliary winding, a first circuit and a second circuit. The power controller is a monolithic integrated circuit with a multi-function pin and a gate pin. A control node of the power switch is coupled to the gate pin. The first circuit is coupled between the multi-function pin and the auxiliary winding and has a diode. The second circuit is coupled between the multi-function pin and a ground line, and has a thermistor. | 11-14-2013 |
20140043081 | SAMPLE-AND-HOLD CIRCUIT FOR GENERATING A VARIABLE SAMPLE DELAY TIME OF A TRANSFORMER AND METHOD THEREOF - A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 002-13-2014 | |
20140233268 | CONTROLLER OF A POWER CONVERTER WITH ADJUSTABLE JITTER AMPLITUDE AND METHOD OF GENERATING ADJUSTABLE JITTER AMPLITUDE THEREOF - A controller of a power converter with adjustable jitter amplitude includes a feedback pin, a logic circuit, an auxiliary pin, and a current sensing pin. The feedback pin is used for receiving a feedback voltage from a secondary side of the power converter. The feedback voltage corresponds to an output voltage of the secondary side of the power converter. The logic circuit is used for generating a jitter signal according to a clock, the feedback voltage, and a first resistor. The auxiliary pin is used for receiving a voltage corresponding to an auxiliary winding of the power converter. The current sensing pin is used for generating a detection voltage according to a current flowing through a primary side of the power converter. The voltage, the jitter signal, and the detection voltage determine turning-on time of the primary side of the power converter. | 08-21-2014 |
20150062970 | CONTROLLERS, POWER SUPPLIES AND CONTROL METHODS - Power supplies together with related over voltage protection methods and apparatuses. A power supply has a transformer including a primary winding and an auxiliary winding. A power switch is coupled to the primary winding and a sensing resistor coupled between the power switch and a grounding line. A multi-function terminal of a controller is coupled to the sensing resistor. A diode and a first resistor is coupled between the auxiliary winding and the multi-function terminal. | 03-05-2015 |
Seng-Chieh Chen, Hsin-Chu TW
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20100141567 | Display Device and Manufacture Method Thereof - The present invention discloses a flat display device and a manufacture method thereof. The flat display device includes a flat display module, a front cover, an auxiliary support, a back cover set, and a circuit board. The back cover set includes a sub-cover and a main back cover, wherein the circuit board is disposed on the inner surface of the sub-cover. The front cover has a display opening for an active area of the flat display module to be exposed outside the display opening and present images through the display opening. The main back cover includes a opening for part of the sub-cover to pass through and be exposed outside the opening. | 06-10-2010 |
Shang Wei Chen, Hsin-Chu TW
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20080237836 | SEMICONDUCTOR CHIP EMBEDDING STRUCTURE - A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the semiconductor chip and the CTE of the dielectric layer. Thereby, the buffer layer can reduce the stress on the interface between the dielectric layer and the semiconductor chip. | 10-02-2008 |
20090200658 | CIRCUIT BOARD STRUCTURE EMBEDDED WITH SEMICONDUCTOR CHIPS - A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured. | 08-13-2009 |
20130286679 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE USING THE SAME - A backlight module includes a light guide plate (LGP), a light source, and at least one prism sheet. The LGP includes a light emitting surface, a bottom surface, a light incident surface, and a plurality of first microstructures on the bottom surface. Each of the first microstructure is a recessed structure and includes a first surface and a second surface. An included angle between the first surface and the bottom surface ranges from 15 degrees to 27 degrees. An included angle between the second surface and the bottom surface ranges from 50 degrees to 90 degrees. The light source provides a light beam, and an included angle between a light emitting direction of the light beam emitted from the light emitting surface of the LGP and a normal direction of the light emitting surface is greater than 30 degrees. The prism sheet is disposed above the light emitting surface. | 10-31-2013 |
20140349027 | TRANSFER PRINTING APPARATUS AND MANUFACTURING METHOD OF LIGHT GUIDING FILM - A transfer printing apparatus includes a mold, a stamper, a pressing roller and a curing unit. The mold has a first surface with first and second concavities, the second concavity has first and second planes, the first plane is perpendicular to the first surface, and the second plane is inclined to the first surface. The stamper having a second surface is disposed in the first concavity. The first and second surfaces are coplanar, and the second surface has transfer printing microstructures. The first and second surfaces are suitable for coated an adhesive layer. The pressing roller presses a base film onto the adhesive layer, such that the adhesive layer is integrated with the base film. The curing unit cures the adhesive layer on the base film, such that a taper corresponding to the second concavity and optical microstructures corresponding to the transfer printing microstructures are formed on the adhesive layer. | 11-27-2014 |
Shan-Nan Chen, Hsin-Chu TW
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20090165316 | Measurement Apparatus Having Display Device - The present invention discloses a measurement apparatus having a display device. The measurement apparatus comprises a control unit, a microprocessing circuit, a display device, and a power supply unit. The control unit is used to change the measurement unit in order to measure different lengths. The measurement apparatus having a display device further comprises a calculating device to provide calculation functionality. | 07-02-2009 |
Shao-Chi Chen, Hsin-Chu TW
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20100097306 | Gamma voltage conversion device - Gamma voltage conversion device includes a gamma voltage conversion circuit, an amplifier, and a gamma voltage adjusting circuit. The gamma voltage conversion circuit generates a first gamma voltage conformed to a first gamma curve according to a grey level. The amplifier includes a first input end receiving the first gamma voltage, a second end, and an output end. The amplifier outputs the first or a second gamma voltage conformed to a second gamma curve according to the grey level according to the first and the second ends of the amplifier. The gamma voltage adjusting circuit coupled between the second input end and the output end of the amplifier controls the amplifier to output the first or the second gamma voltage as the gamma driving voltage according to the grey level and a gamma curve selection signal. | 04-22-2010 |
Shih-Huang Chen, Hsin-Chu TW
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20090090849 | Image detectors and image detection modules - An image detector comprising a first detection array and a second detection array. The first detection array comprises a plurality of first detection units disposed sequentially, and each first detection unit comprises a plurality of first detection cells. In each first detection unit, the first detection cells respectively generate a plurality of first signals, and the first signals respectively represent different color information. The second detection array comprises a plurality of second detection units disposed sequentially, and each second detection unit comprises at least one second detection cells. Each second detection cell generates a second signal, and each second signal represents specific color information. | 04-09-2009 |
20090310008 | DETECTION DEVICES - A detection device for detecting an object image comprises a detection unit and a read-out unit. The detection unit comprises at least one detection array. The at least one detection array comprises a plurality of detection cells disposed in M detection rows, M≧2. The detection cells generate a plurality of detection signals, and the detection signals represent specific color information. The read-out unit receives the detection signals from the at least one detection array and generates an image signal according to the received detection signals. | 12-17-2009 |
20120158690 | SYSTEMS AND METHODS FOR NETWORK SEARCHES INTEGRATED WITH IMAGE SENSOR MODULE - A method for network search integrated with an image sensor module is provided for an electric apparatus. An image is obtained by the image sensor module, wherein the image sensor module is coupled to the electric apparatus. The image is automatically inputted to an input field of a search engine, so as to search the image via a network. | 06-21-2012 |
20120229821 | INTEGRATED CONTACT IMAGE SENSOR MODULE AND IMAGE SCANNING SYSTEM - An integrated contact image sensor module (CISM) is provided. A light switch circuit turns on a light source according to a light control signal. A contact image sensor captures an image when the light source is turned on and generates an analog signal corresponding to the image. An analog to digital converter coupled to the contact image sensor converts the analog signal into scan data. A controller coupled to the light switch circuit provides the light control signal to the light switch circuit according to a motion signal and provides a clock signal to the analog to digital converter, so as to convert the analog signal into the scan data. The controller further provides an interface signal corresponding to the scan data, to an interface module according to the motion signal, and the interface signal conforms to a specific transmission protocol. | 09-13-2012 |
Shin Chang Chen, Hsin-Chu TW
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20090217994 | Multi-channel fluid conveying apparatus - A multi-channel fluid conveying apparatus, for delivering a fluid, includes a valve seat, a valve cover, a valve membrane, a plurality of temporary-deposit chambers, and an actuating device. The valve seat includes at least one inlet channel and at least one outlet channel. The valve cover is arranged on the valve seat. The valve membrane is interposed between the valve seat and the valve cover and includes a plurality of valve structures made of the same material with the same thickness, wherein at least one of the valve structures has a rigidity different from those of other valve structures. The plurality of temporary-deposit chambers is interposed between the valve membrane and the valve cover and between the valve membrane and the valve seat. The actuating device is, having a periphery, fixed to the valve cover. | 09-03-2009 |
Shin-Shueh Chen, Hsin-Chu TW
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20100244033 | OPTICAL SENSOR, METHOD OF MAKING THE SAME, AND DISPLAY PANEL HAVING OPTICAL SENSOR - An optical sensor, method of making the same, and a display panel having an optical sensor. The optical sensor includes a first electrode, a second electrode, a photosensitive silicon-rich dielectric layer, and a first interfacial silicon-rich dielectric layer. The photosensitive silicon-rich dielectric layer is disposed between the first and second electrodes. The first interfacial silicon-rich dielectric layer is disposed between the first electrode and the photosensitive silicon-rich dielectric layer. | 09-30-2010 |
20140332799 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate electrode, an insulating layer, a source electrode, a drain electrode, a semiconductor channel layer, a first passivation layer and a second passivation layer. The gate is formed on the substrate. The insulating layer covers the gate electrode. The source electrode and the drain electrode are positioned on the insulating layer. The semiconductor channel layer is disposed on the insulating layer, and connects the source electrode and the drain electrode. The first passivation layer covers the source electrode, the drain electrode and the semiconductor channel layer. The first passivation layer includes silicon oxide. The second passivation layer is disposed on the first passivation layer. The second passivation layer includes silicon nitride that has a hydrogen concentration of about 2.0×10 | 11-13-2014 |
Shiow-Hui Chen, Hsin-Chu TW
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20100011540 | Pliable handle - A pliable handle is defomable as it being held. When the force is released, the pliable handle will retain a deformed shape temporarily and return to an original shape gradually. The pliable handle comprises a middle rod, a lower rod below the middle rod; the lower rod having a buckling seat and an upper position plate; an upper positioning trench being formed between the buckling seat and the upper positioning plate; a plastic cover enclosing around the lower rod; the plastic cover encloses the thin bag containing gel so as to form a space between the lower rod and the thin bag, which is allowed to be wrapped around with several circles; and a base combined to the lower rod and tightly engaging a lower edge of the plastic cover. | 01-21-2010 |
Shou-Chih Chen, Hsin-Chu TW
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20110051099 | ADJUSTING MECHANISM, PROJECTOR, ELECTRONIC WHITEBOARD, AND ADJUSTING METHODS OF PROJECTOR AND ELECTRONIC WHITEBOARD - An electronic whiteboard includes a projection unit, an adjusting mechanism, and a projection screen. The adjusting mechanism includes a fixing base, a rotary plate, and a first screw. The fixing base is adapted to be fixed to a fixing object. The rotary plate is pivotally connected to the fixing base, and is ball jointed to the projection unit. The first screw is locked on the rotary plate, and is ball jointed to the projection unit. The first screw drives the projection unit to rotate relatively to the rotary plate along a first axis when the first screw is rotated. The projection screen is adapted to be fixed to the fixing object. The projection unit is capable of projecting an image beam onto the projection screen. | 03-03-2011 |
Shui-Hunyi Chen, Hsin-Chu TW
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20090101937 | NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION - The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices. | 04-23-2009 |
Sung-Nan Chen, Hsin-Chu TW
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20090231549 | BEAM COMBINING DEVICE AND PROJECTOR HAVING SUCH BEAM COMBINING DEVICE - A beam combining device and a projector having such a beam combining device are provided. The projector includes a first color light source, a second color light source, a third color light source, a beam combining device, a light valve and a projection unit. The first color light source, the second color light source and the third color light source respectively emit first, second and third color beams. The beam combining device includes a polarization state converting module, a color separation unit and a polarization beam splitter. The optical path lengths of the first color beam emitted from the first color light source to the polarization beam splitter, the second color beam emitted from the second color light source to the polarization beam splitter, and the third color beam emitted from the third color light source to the polarization beam splitter are equal. | 09-17-2009 |
20110002051 | Fixed focus lens and imaging system - A fixed-focus lens capable of imaging a light valve disposed at a reduced side onto a magnified side is provided. The fixed-focus lens includes a first lens group, a second lens group, and a free form reflective mirror. The first lens group is disposed in the light path between the reduced side and the magnified side. The second lens group is disposed in the light path between the first lens group and the magnified side and includes a first free form lens. The free form reflective mirror is disposed in the light path between the second lens group and the magnified side. An imaging surface imaged from the light valve by the fixed-focus lens is a curved surface. An imaging system using the fixed-focus lens is also provided. | 01-06-2011 |
S-Wei Chen, Hsin-Chu TW
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20100110389 | Laser projection system - A laser projection system includes a plurality of laser light sources, a light combining module, an image generating module, a lens, a diffusion module. and a projection lens. The laser light sources are used to provide a plurality of light beams with different colors. The light combining module is disposed in the light path of the laser beams for mixing the laser beams to form a mixing light beam. The image generating module is disposed in the light path of the mixing light beam for receiving the mixing light beam to generate a first image. The lens is disposed in the light path of the first image and provides an imaging position. The first image passes through the lens to form a second image at the imaging position. The diffusion module includes a diffuser and an actuator. The projection lens projects the second image on a screen. | 05-06-2010 |
20110096298 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS - An illumination system includes a chip package, a first dichroic film, a second dichroic film, and a third dichroic film. The first dichroic film, the second dichroic film, and the third dichroic film are not parallel to each other and do not cross each other. The chip package includes a first light-emitting chip capable of emitting a first light beam, a second light-emitting chip capable of emitting a second light beam, and a third light-emitting chip capable of emitting a third light beam. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are arranged in a row. The first dichroic film reflects the first light beam and transmitting the second light beam, the second dichroic film reflects the second light beam, the first dichroic film and the second dichroic film transmit the third light beam, and the third dichroic film reflects the third light beam. | 04-28-2011 |
20110096299 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS HAVING THE SAME - An illumination system includes a chip package, a first dichroic film, a second dichroic film, and a third dichroic film. The first dichroic film, the second dichroic film, and the third dichroic film are not parallel to each other and cross one another at an identical region. The chip package includes a first light-emitting chip capable of emitting a first light beam, a second light-emitting chip capable of emitting a second light beam, and a third light-emitting chip capable of emitting a third light beam. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are arranged to form a delta arrangement. The first dichroic film is capable of reflecting the first light beam, and the second dichroic film is capable of reflecting the second light beam. The first dichroic film is capable of transmitting the third light beam, and the third dichroic film is capable of reflecting the third light beam. | 04-28-2011 |
Tai-Cheng Chen, Hsin-Chu TW
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20100141567 | Display Device and Manufacture Method Thereof - The present invention discloses a flat display device and a manufacture method thereof. The flat display device includes a flat display module, a front cover, an auxiliary support, a back cover set, and a circuit board. The back cover set includes a sub-cover and a main back cover, wherein the circuit board is disposed on the inner surface of the sub-cover. The front cover has a display opening for an active area of the flat display module to be exposed outside the display opening and present images through the display opening. The main back cover includes a opening for part of the sub-cover to pass through and be exposed outside the opening. | 06-10-2010 |
Tien-Pao Chen, Hsin-Chu TW
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20100149498 | Image display apparatus - An image display apparatus includes a screen, a reflection mirror, an adaptive optics, and a projection unit. The reflection mirror has a reflective surface facing a light incident surface of the screen, and is separated from the light incident surface by a space. The boundary of the space is defined by the edges of the reflective surface and the light incident surface. The adaptive optics is disposed on the boundary of the space. The projection unit is disposed outside the space. The adaptive optics has a light exit side facing the reflective surface of the reflection mirror, and a light incident side facing the projection unit. A projecting light is generated from the projection unit, passes through the adaptive optics for adjusting the image size formed by the projecting light, and then is projected to the reflective surface of the reflection mirror for being reflected to the light incident surface. | 06-17-2010 |
Tung-Huang Chen, Hsin-Chu TW
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20100134463 | Driving Method of Display Panel with Half-Source-Driving Structure - An exemplary driving method of a display panel with half-source-driving structure is provided. The display panel includes at least one pixel each using a capacitor to store a voltage. A terminal of the capacitor is adapted to receive a display data inputted from a data line, and another terminal of the capacitor is electrically coupled to a common electrode. The driving method includes: obtaining a direct current power signal; coupling an alternating current signal with the direct current power signal to generate a common electrode driving signal; and applying the common electrode driving signal to the common electrode. A rising time of a rising edge and a falling time of a falling edge of the common electrode driving signal are modified to improve a V-line mura phenomenon of the display panel. | 06-03-2010 |
Wei-Ju Chen, Hsin-Chu TW
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20100045946 | Projection Apparatus - A projection apparatus includes a housing, a switch unit, a projection module, a circuit unit and a remote controller. The housing has an accommodation space and a containing groove. The switch unit is arranged in the containing groove. The projection module and the circuit unit are arranged in the accommodation space, and the circuit unit is electrically connected to the projection module and the switch unit. The remote controller is adapted to be contained in the containing groove and be taken out from the containing groove. When the remote controller is contained in the containing groove, the remote controller contacts the switch unit, and the circuit unit enables and disables the projection module according to a contact relation between the remote controller and the switch unit. The remote controller of the projection apparatus is easy to be contained. | 02-25-2010 |
20110128504 | ADJUSTMENT DEVICE AND PROJECTOR HAVING THE SAME - An adjustment device for adjusting an angle of a dichroic mirror of a projector with respect to an optical engine base of the projector is disclosed. The dichroic mirror is pivotably mounted to the optical engine base. The adjustment device includes a link and an eccentric screw. The link has a first end and a second end. The first end is adapted to be fixedly mounted to the dichroic mirror. The second end has an opening. The eccentric screw is adapted to extend through the opening to be screwed to the optical engine base. The eccentric screw includes an eccentric section disposed within the opening. The eccentric section pushes the link such that the link drives the dichroic mirror to pivot with respect to the optical engine base upon rotating of the eccentric screw. A projector including the adjustment device is also disclosed. | 06-02-2011 |
20120091306 | PROJECTION DEVICE - A projection device including a turntable module and a projection module is provided. The turntable module includes a first turntable and a second turntable. The first turntable is disposed on a surface. The second turntable is disposed on the first turntable and connected to the first turntable, and rotates relative to the first turntable by revolving along a rotation axis. The projection module is disposed on the turntable module and fixed to the second turntable. | 04-19-2012 |
Wei-Ta Chen, Hsin-Chu TW
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20100117708 | Voltage Level Converter without Phase Distortion - A voltage level converter with reduced signal phase distortion is provided. The voltage level converter includes a level shifting circuit followed by a unit interval retrieval circuit. The level shifting circuit takes complementary input voltage signals and converts to signals with different voltage levels. The unit interval retrieval circuit responds to the output complementary signals from the level shifting circuit and generates one or more output signals that restore the period of the original input voltage signals with no or negligible phase distortion. | 05-13-2010 |
Wu-Min Chen, Hsin-Chu TW
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20100045631 | MATRIX SENSING APPARATUS - A matrix sensing apparatus with architecture having reduced quantity of required sensing lines is disclosed. The matrix sensing apparatus includes a plurality of driving lines, a plurality of sensing lines and a matrix sensing region. The matrix sensing region includes a plurality of sensing areas. Each sensing area includes a first transistor, a second transistor, and a sensing unit for generating a sensing signal. The first transistor is coupled to the sensing unit and a corresponding sensing line. The second transistor is coupled to the first transistor, a first corresponding driving line and a second corresponding driving line. The first transistor together with the second transistor functions to control the signal connection between the sensing unit and the corresponding sensing line based on the driving signals of the first and second corresponding driving lines. | 02-25-2010 |
Yen-Si Chen, Hsin-Chu TW
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20110076401 | Method of Making Showerhead for Semiconductor Processing Apparatus - A method of making a showerhead for a semiconductor processing apparatus is disclosed. In one embodiment, the method includes providing a substrate; forming first holes in the substrate; forming a protective film on the substrate, where the protective film covers sidewalls of the first holes; and forming second holes in the substrate, where a part of the protective film within the first holes is removed. In another embodiment, the method includes providing a substrate; forming islands on the substrate; forming a protective film on the substrate, where the protective film does not cover the tops of the islands; and forming holes in the islands. | 03-31-2011 |
Yi-Chan Chen, Hsin-Chu TW
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20100140583 | PHASE CHANGE MEMORY DEVICE AND FABRICATING METHOD THEREFOR - A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer. | 06-10-2010 |
Yi-Jan Chen, Hsin-Chu TW
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20100164724 | Amplitude Shift Keying Demodulator and Radio Frequency Identification System using the same - An exemplary amplitude shift keying (ASM) demodulator and a radio frequency identification (RFID) system using the same are provided. The ASM demodulator is adapted to demodulate an alternating current input signal and generate a demodulated envelope signal. The ASM demodulator includes a signal input terminal group, an input rectifier circuit, a current mirror circuit electrically coupled to the input rectifier circuit, an output stage electrically coupled to the current mirror circuit, and a low pass filter electrically coupled to the output stage. The input rectifier circuit is electrically coupled to the signal input terminal group and adapted to perform a rectifying operation applied to the alternating current input signal. The input rectifier circuit includes a plurality of electrically coupled transistors and a gate electrode of each of the transistors is unconnected with a source electrode and a drain electrode itself. | 07-01-2010 |
Ying-Chao Chen, Hsin-Chu TW
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20090153791 | Chip on film structure - The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge. | 06-18-2009 |
Yi-Tzu Chen, Hsin-Chu TW
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20100165749 | Sense Amplifier Used in the Write Operations of SRAM - A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation. | 07-01-2010 |
20100165767 | Asymmetric Sense Amplifier - Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier. | 07-01-2010 |
20100185904 | System and Method for Fast Cache-Hit Detection - A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator. | 07-22-2010 |
20100201454 | VDD-Independent Oscillator Insensitive to Process Variation - An oscillator includes a positive power supply node for providing a positive power supply voltage; a capacitor; and a constant current source providing a first constant current and coupled to the positive power supply node. The first constant current is independent from the positive power supply node. The oscillator also includes a charging current source configured to provide a second constant current to charge the capacitor, wherein the second constant current mirrors the first constant current. The oscillator further includes a constant current source inverter having a third constant current mirroring the first constant current. The constant current source inverter is configured to control the oscillator to transition state at a constant state transition voltage. | 08-12-2010 |
20100260002 | Circuit and Method for Small Swing Memory Signals - Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time. | 10-14-2010 |
20110317506 | Method for Asymmetric Sense Amplifier - Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed. | 12-29-2011 |
20120023388 | Parity Look-Ahead Scheme for Tag Cache Memory - A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit. | 01-26-2012 |
20120026818 | Split Bit Line Architecture Circuits and Methods for Memory Devices - Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved. | 02-02-2012 |
20120098582 | Flip-Flop Circuit Design - A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal. | 04-26-2012 |
20120317374 | SRAM Multiplexing Apparatus - An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer. | 12-13-2012 |
20120327705 | Data-Aware SRAM Systems and Methods Forming Same - Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively. | 12-27-2012 |
20130328636 | VDD-Independent Oscillator Insensitive to Process Variation - A method of providing an oscillating signal, comprising providing a first constant current flowing from a positive power supply node, the first constant current independent of a variation in a positive power supply node voltage, providing a second constant current flowing from a positive power supply node to a second electrode of a capacitor, a first electrode of the capacitor connected directly to the positive power supply node, the second constant current mirroring the first constant current and charging the capacitor by reducing a voltage across the capacitor. A third constant current is provided flowing from the positive power supply node through a first NMOS transistor and mirroring the first constant current, the first NMOS transistor having a gate connected directly to the second electrode of the capacitor and an oscillating signal generated by turning on the first NMOS transistor when the capacitor reaches a predetermined voltage level. | 12-12-2013 |
20140119104 | Data-Aware SRAM Systems and Methods Forming Same - Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively. | 05-01-2014 |
20140233303 | SRAM Multiplexing Apparatus - An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer. | 08-21-2014 |
Yung-Jen Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20090102991 | Liquid Crystal Display Panel - A liquid crystal display panel is provided. The liquid crystal display panel includes a plurality of pixel units, a first common voltage region and a second common voltage region. The pixel units include a first group of pixel units and a second group of pixel units arranged in rows and columns. The first common voltage region carries a first alternating current thereon and is electrically connected to the first group of pixel units. The second common voltage region carries a second alternating current thereon and is electrically connected to the second group of pixel units. | 04-23-2009 |
20140333688 | DISPLAY PANEL AND DRIVING METHOD THEREOF - A display panel includes a plurality of pixels, each of the pixels including a main sub-pixel and a secondary sub-pixel; a plurality of first scan lines, each of the first scan lines being coupled to main and secondary sub-pixels of a row of pixels; a plurality of second scan lines, each of the second scan lines being coupled to secondary sub-pixels of a row of pixels; a plurality of first data lines, each of the first data lines being coupled to main and secondary sub-pixels of (N+1)th and (N+2)th rows of pixels; a plurality of second data lines, each of the second data lines being coupled to main and secondary sub-pixels of (N+3)th and (N+4)th rows of pixels; a scan driver for turning on the main and secondary sub-pixels of the pixels; and a data driver for outputting data signals; wherein N is a multiple of 4, and N≧0. | 11-13-2014 |
Yu-Yu Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20110134366 | Backlight Module and Display Device Having the Same - The present invention discloses a backlight module and a display device comprising the backlight module. The backlight module includes a light source, a light guide plate and a frame, wherein the light guide plate has a light entrance end and a first side. An angle is included between the light entrance end and the first side, wherein a plurality of light diffusing structures are formed on the light entrance end. The light source is disposed at a position corresponding to the light entrance end and emits a light toward the light diffusing structures. The frame has a first wall facing an inner surface of the first side. A centre line perpendicular to the light entrance end is defined on the light guide plate, wherein the distance between the inner surface and the centre line increases in a direction toward the light source. | 06-09-2011 |
20120155111 | BACKLIGHT MODULE - A reflective back cover made of plastic material having micro cellular structures is processed by compression molding and cutting so as to have a monolithical structure. The white material of the reflective back cover reflects lights such that the back cover can be an integral component featuring multiple functions of various components. With the thickness control of the reflective back cover, a concave can be formed at the side of the back cover where a light source is contained and the concave further retains the light source and its flexible printed circuit board. With the incorporation of the reflective back cover, the thickness of the backlight module can be reduced and a reliable and repetitive manufacturing of the backlight module can be introduced. | 06-21-2012 |
20140321154 | BACKLIGHT MODULE - A reflective back cover made of plastic material having micro cellular structures is processed by compression molding and cutting so as to have a monolithical structure. The white material of the reflective back cover reflects lights such that the back cover can be an integral component featuring multiple functions of various components. With the thickness control of the reflective back cover, a concave can be formed at the side of the back cover where a light source is contained and the concave further retains the light source and its flexible printed circuit board. With the incorporation of the reflective back cover, the thickness of the backlight module can be reduced and a reliable and repetitive manufacturing of the backlight module can be introduced. | 10-30-2014 |
Zeng-De Chen, Hsin-Chu TW
Patent application number | Description | Published |
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20100026658 | TOUCH SUBSTRATE OF EMBEDDED TOUCH DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - An embedded touch display panel including a first substrate and a second substrate is provided. The first substrate having a displaying region and a sensing region includes a stack structure, a first conductive layer and a first alignment layer. The stack structure disposed on the first substrate within the sensing region includes a protruding structure and a first rough structure disposed on the protruding structure. The first conductive layer conformally disposed on the stack structure has a first rough surface. The first rough surface is exposed from the first alignment layer that covers the first conductive layer. The second substrate includes a second conductive layer and a second alignment layer. The second conductive layer whose position corresponds to the sensing region is disposed on the second structure. A portion of the second conductive layer corresponding to the first rough surface is exposed from the second alignment layer covering thereon. | 02-04-2010 |
20100109988 | Display Apparatus - A display apparatus is disclosed, and comprises a display panel and a lens. On the display panel, there are a width-fixed pixel zone, a width-variating pixel zone and a border zone arranged sequentially from the center to the edges of the display panel, wherein there are a plurality of width-fixed pixels disposed in the width-fixed zone, and there are a plurality of width-variating pixel groups disposed in the width-variating pixel zone, and the widths of the width-variating pixel groups are present in a first decreasing sequence. The lens has a focus-length-variating portion and a planar portion, wherein the planar portion is aligned with the width-fixed pixel zone, and the focus-length-variating portion is disposed to correspond to the border zone and the width-variating pixel zone. The focus lengths of the focus-length-variating portion corresponding to the width-variating pixel groups are present in a second decreasing sequence. | 05-06-2010 |
20100220068 | Method for Mitigating Pooling Mura on Liquid Crystal Display Apparatus and Liquid Crystal Display Apparatus - A method for mitigating pooling mura on LCD apparatus and a LCD apparatus are provided. The method is adapted for a LCD apparatus having a plurality of pixels. The LCD apparatus is for displaying frames according to a received original display data, and each of at least a part of the pixels comprises two pixel electrodes to drive a plurality of liquid crystal molecules between the two pixel electrodes. The method comprises changing a corresponding portion of the original display data so as to rotate at least a part of the liquid crystal molecules between the two pixel electrodes of the pressed pixel toward a natural angle; and maintaining another corresponding portion of the original display data. The natural angle is a finally-presented tilt angle of the liquid crystal molecules between the corresponding two pixel electrodes having substantially no potential difference therebetween. | 09-02-2010 |
20110157061 | Touch-Sensing Display Device and Touch-Sensing Module Thereof - A touch-sensing display device, specifically to a borderless touch-sensing display device, is disclosed. The touch-sensing display device includes a display module and a touch-sensing module. The touch-sensing module includes a first sensing sheet and a second sensing sheet, wherein a space exists between the first sensing sheet and the second sensing sheet. The first sensing sheet includes a lens layer, a plurality of first conductive portions, and a conductive film, wherein the conductive film is disposed on the lens layer while the first conductive portions are distributed on two opposite sides of the lens layer. The second sensing sheet includes a substrate, a plurality of second conductive portions, and a plurality of conductive strips, wherein the second conductive portions are selectively distributed on one of two sides of the substrate while the conductive strips are respectively connected to the second conductive portions and have different voltages. | 06-30-2011 |
20110304563 | TOUCH DISPLAY PANEL AND TOUCH SENSOR STRUCTURE THEREOF - A touch sensor structure includes a first substrate, a second substrate, a first stage, and a conductive spacer. The first substrate and the second substrate are disposed oppositely. The first stage is disposed on the first substrate, facing the second substrate. The first stage includes at least one supporting structure, a sensing structure, and a conductive sensing pad disposed on the sensing structure. The conductive spacer is disposed on the second substrate, facing the first substrate, where the conductive spacer is corresponding to the first stage. | 12-15-2011 |