Patent application number | Description | Published |
20140353833 | Stress Compensation Layer to Improve Device Uniformity - The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices. | 12-04-2014 |
20140374832 | BEOL SELECTIVITY STRESS FILM - The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance. | 12-25-2014 |
20150048507 | CONDUCTIVE DIFFUSION BARRIER STRUCTURE FOR OHMIC CONTACTS - An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region. | 02-19-2015 |
20150069395 | Smart Measurement Techniques to Enhance Inline Process Control Stability - An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred. | 03-12-2015 |
20150206845 | INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME - Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure. | 07-23-2015 |
20150255394 | SEMICONDUCTOR DEVICE WITH SELF-PROTECTING FUSE AND METHOD OF FABRICATING THE SAME - A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented. | 09-10-2015 |
20150279769 | CHIP PACKAGE, USE AND METHOD OF MAKING THEREO - A method of forming a chip package portion having a reduced loading effect between various metal lines during a leveling process comprises forming a first layer, a passivation layer over the first layer, a second layer over the passivation layer, and a third layer over the second layer. The method also comprises forming a patterned opening having multiple depths by removing portions of the first layer, the passivation layer, the second layer, and the third layer by way of one or more removal processes that remove portions of the first layer, the passivation layer, the second layer, and the third layer in accordance with one or more patterned photoresist depositions. The method further comprises depositing a material into the patterned opening, and leveling the material deposited into the patterned opening | 10-01-2015 |
20150311156 | SYSTEMS AND METHODS TO ENHANCE PASSIVATION INTEGRITY - A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids. | 10-29-2015 |