| Patent application number | Description | Published |
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| 20090006809 | NON-DISRUPTIVE CODE UPDATE OF A SINGLE PROCESSOR IN A MULTI-PROCESSOR COMPUTING SYSTEM - Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor is terminated whereby all processes and threads being executed by the first processor are terminated. Execution of a self-reset of the first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor. | 01-01-2009 |
| 20130326266 | Maximizing Use of Storage in a Data Replication Environment - Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device. | 12-05-2013 |
| 20130326270 | Maximizing Use of Storage in a Data Replication Environment - Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device. | 12-05-2013 |
| 20140095789 | MANAGEMENT OF DATA USING INHERITABLE ATTRIBUTES - Embodiments relate to a system and computer program product for data management. An aspect includes a method for assigning storage types to data based on access frequency. Past or historical data associated with current data usage is also considered prior to assignment. Once data frequency access is determined, the current data is assigned to a first tier of a plurality of hierarchical ordered tiers, each tier corresponding to at least one class of storage. In one embodiment, there may be a condition that overrides the assignment with option to override it. The tier assignment may also be preserved so that the current data can be appropriately assigned in the future. | 04-03-2014 |
| 20140095790 | MANAGEMENT OF DATA USING INHERITABLE ATTRIBUTES - Embodiments relate to a method for data management. An aspect includes a method for assigning storage types to data based on access frequency. Past or historical data associated with current data usage is also considered prior to assignment. Once data frequency access is determined, the current data is assigned to a first tier of a plurality of hierarchical ordered tiers, each tier corresponding to at least one class of storage. In one embodiment, there may be a condition that overrides the assignment with option to override it. The tier assignment may also be preserved the tier so that the current data can be appropriately assigned in the future. | 04-03-2014 |
| 20140351537 | MAPPING A SOURCE WORKLOAD PATTERN FOR A SOURCE STORAGE SYSTEM TO A TARGET WORKLOAD PATTERN FOR A TARGET STORAGE SYSTEM - Provided are a method, system, and computer program product for mapping a source workload pattern for a source storage system to a target workload pattern for a target storage system. A source workload pattern is received from the source storage system having workload access characteristics of source logical addresses at the source storage system. The source workload pattern at the source logical addresses is mapped to a target workload pattern for target logical addresses at the target storage system. The target workload pattern for the target workload addresses is provided to the target storage system to use to determine storage locations in the target storage system to store received replicated data from the source logical addresses at the target logical addresses. | 11-27-2014 |
| 20150082079 | Maximizing Use of Storage in a Data Replication Environment - Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device. | 03-19-2015 |
| 20150089277 | Maximizing Use of Storage in a Data Replication Environment - Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device. | 03-26-2015 |
| 20150100776 | NON-DISRUPTIVE CODE UPDATE OF A SINGLE PROCESSOR IN A MULTI-PROCESSOR COMPUTING SYSTEM - Updating code of a single processor in a multi-processor system includes commencing of a self-reset of a first processor if a bit is found in a first state, and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor. | 04-09-2015 |
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| 20080276017 | SYSTEM AND ARTICLE OF MANUFACTURE FOR THE DETECTION OF MISDIRECTED DATA - Provided are a system and article of manufacture, wherein in certain embodiments an I/O command from a host is received at a first storage unit. An identifier is generated that identifies a destination to which the I/O command is to be transmitted from the first storage unit. The I/O command is augmented with the generated identifier at the first storage unit. The augmented I/O command is transmitted. In certain other embodiments, an I/O command is received at a storage unit, wherein the storage unit is associated with a storage unit identifier. A determination is made at the storage unit, whether the I/O command is associated with an identifier that identifies a destination for which the I/O command is intended. A further determination is made, at the storage unit, whether the identifier is the same as the storage unit identifier, in response to determining that the identifier associated with the I/O command identifies the destination for which the I/O command is intended. | 11-06-2008 |
| 20090013099 | SYSTEM AND PROGRAM FOR TRANSMITTING INPUT/OUTPUT REQUESTS FROM A FIRST CONTROLLER TO A SECOND CONTROLLER - Provided are a method, system, and program monitoring paths between a first controller and second controller. A determination is made as to whether one path has been unavailable for a predetermined time period in response to detecting that the path is unavailable. Indication is made that the path is in a first failed state if the path has been unavailable for more than the predetermined time period and indication is made that the path is in a second failed state if the path has not been unavailable for the predetermined time period. | 01-08-2009 |
| 20090049251 | SPLITTING WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. | 02-19-2009 |
| 20090049252 | REPLICATION ENGINE COMMUNICATING WITH A SPLITTER TO SPLIT WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for a replication engine communicating with a splitter to split writes between a storage controller and replication engine. Communication is initiated with the splitter implemented in a storage controller managing access to primary volumes. A command is sent to the splitter to copy writes to one primary volume to the replication engine. Write data is received from the splitter to one of the primary volumes following the splitter receiving the command to copy the writes to the replication engine. A determination is made of a copy services function to use for the received data. The determined copy services function is invoked to transfer the received data to a secondary storage volume. | 02-19-2009 |
| 20090089791 | RESOURCE ALLOCATION UNIT QUEUE - Provided is a system, deployment and program for resource allocation unit queuing in which an allocation unit associated with a task is classified. An allocation unit freed as the task ends is queued for use by another task in a queue at a selected location within the queue in accordance with the classification of said allocation unit. In one embodiment, an allocation unit is queued at a first end of the queue if classified in a first class and is queued at a second end of the queue if classified in said second class. Other embodiments are described and claimed. | 04-02-2009 |
| 20120124310 | SPLITTING WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. | 05-17-2012 |
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| 20090287402 | VIRTUAL TRAFFIC SENSORS - Techniques are described for virtual traffic sensors (VTS). In an implementation, an electronic device provides a variety of functionality including at least functionality to determine position. The electronic device may be further configured to ascertain locations of one or more virtual traffic sensors. In at least some embodiments, locations of virtual traffic sensors are determined by the electronic device using a variety of VTS criteria. Using a determined position, the electronic device may detect proximity to the virtual traffic sensors. The electronic device may collect traffic related data when in proximity to the one or more virtual traffic sensors. The electronic device may then communicate the collected traffic data over a suitable network connection to a service provider. | 11-19-2009 |
| 20090287405 | TRAFFIC DATA QUALITY - Techniques are described for traffic data quality. In an implementation, an electronic device provides a variety of functionality including functionality to determine position. The device may use determined position to ascertain geographic locations as collection points where traffic related data may be collected. In at least some embodiments, traffic data quality techniques combining both device side and server side technique are applied to data collected at the collections points. In an embodiment, communication of collected data by the device may be delayed to enable additional observations of vehicle movement, routing, position, and so forth. The additional observations during the delay enable the device to determine the validity of the collected data. | 11-19-2009 |
| 20100049397 | FUEL EFFICIENT ROUTING - Techniques are described to determine a fuel-efficient route for a vehicle. In an implementation, a determination is made, based on the one or more characteristics of the vehicle, as to a route between an identified location and a designated location that would cause the vehicle to consume a lesser amount of fuel when traveling between the identified and designated locations. Accordingly, the route may be represented, such as for use in navigating to the designated location. | 02-25-2010 |
| 20110153189 | HISTORICAL TRAFFIC DATA COMPRESSION - A device and method for calculating information regarding a route to a destination. The device may include a computer-readable memory element on which is stored a plurality of templates comprising historical speed values for a quantity of time segments and a map database including data for a plurality of road segments associated with template codes identifying one or more of the templates. The device may also include a processing device for accessing the map database to determine a historical speed value for one or more selected road segments. The historical speed value may be used for calculating an estimated amount of time to complete a selected route, a route to the destination that takes the least amount of time, and/or a predicted time of arrival at the destination. | 06-23-2011 |
| 20110207455 | METHOD AND APPARATUS FOR ESTIMATING CELLULAR TOWER LOCATION - A method and apparatus for collecting and analyzing cellular identification (ID) numbers at various geographic locations to estimate cellular tower locations. The method may include collecting cellular ID numbers obtained by collection mobile devices at a plurality of geographic locations then calculating minimum bounding circles encompassing a set of geographic location points with the same cellular identification numbers. If the cellular ID number of a set of location points indicates that the cellular tower is omni-directional, a center of the minimum bounding circle is an estimated cellular tower location. If the cellular ID number indicates that the cellular tower is multi-sector, the apparatus may calculate the estimated cellular tower location as the location at which lines that extend from the centers of a plurality of related minimum bounding circles intersect with each other to form equal angles. | 08-25-2011 |
| 20120124125 | AUTOMATIC JOURNAL CREATION - Techniques are described that facilitate the automatic creation of journals that may include a variety of related content. Journal creation functionality may be furnished by a server to one or more client devices to create journals of content that include content from one or more content sources. The content provided by the content sources includes tags (e.g., metadata) describing the content. Thus, a client device may furnish a request to a server to create a journal of content. The request includes an attribute to relate the content of the journal. The server causes content to be associated with the journal from one or more computer-readable content sources accessible by the server by associating one or more of the content tags with the attribute for one or more existing journals and thereafter creating the journal using the processor by causing content from the one or more existing journals to be associated with the journal, the associated content having tags associated with the attribute. | 05-17-2012 |
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| 20090127587 | TUNABLE ANTIFUSE ELEMENTS - A tunable antifuse element ( | 05-21-2009 |
| 20090267127 | Single Poly NVM Devices and Arrays - A single-poly non-volatile memory includes a PMOS select transistor ( | 10-29-2009 |
| 20090290437 | CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE - A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device. | 11-26-2009 |
| 20110261500 | BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein. | 10-27-2011 |
| 20110299337 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-08-2011 |
| 20130270606 | Semiconductor Device with Integrated Breakdown Protection - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 10-17-2013 |
| 20130270635 | Semiconductor Device with False Drain - An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic. | 10-17-2013 |
| 20130341717 | Semiconductor Device with Floating RESURF Region - A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap. | 12-26-2013 |
| 20140001473 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
| 20140001477 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
| 20140001546 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
| 20140001548 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
| 20140001549 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
| 20140001594 | SCHOTTKY DIODE WITH LEAKAGE CURRENT CONTROL STRUCTURES | 01-02-2014 |
| 20140061715 | ZENER DIODE DEVICE AND FABRICATION - A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region. | 03-06-2014 |
| 20140061731 | Tunable Schottky Diode - A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region. | 03-06-2014 |
| 20140242762 | Tunable Schottky Diode with Depleted Conduction Path - A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed. | 08-28-2014 |
| 20140252470 | Semiconductor Device with Integrated Electrostatic Discharge (ESD) Clamp - A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively. | 09-11-2014 |
| 20140252472 | SEMICONDUCTOR DEVICE WITH INCREASED SAFE OPERATING AREA - A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well. | 09-11-2014 |
| 20140375370 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-25-2014 |
| 20150085407 | STACKED PROTECTION DEVICES AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface. | 03-26-2015 |
| 20150162417 | ZENER DIODE DEVICES AND RELATED FABRICATION METHODS - Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different. | 06-11-2015 |
| 20150316503 | Differential Pair Sensing Circuit Structures - A differential pair sensing circuit ( | 11-05-2015 |
| 20150333189 | ZENER DIODE DEVICES AND RELATED FABRICATION METHODS - Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different. | 11-19-2015 |
| 20150357324 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 12-10-2015 |
| 20150380317 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 12-31-2015 |
| 20160099240 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING - A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region. | 04-07-2016 |
| 20160099349 | SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION - A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices. | 04-07-2016 |
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| 20140218829 | ELECTROSTATIC DISCHARGE CIRCUIT - An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit. | 08-07-2014 |
| 20140252552 | SEMICONDUCTOR DIES HAVING SUBSTRATE SHUNTS AND RELATED FABRICATION METHODS - Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device. | 09-11-2014 |
| 20140346560 | PROTECTION DEVICE AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage. | 11-27-2014 |
| 20140347771 | PROTECTION DEVICE AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region. | 11-27-2014 |
| 20150021739 | PROTECTION DEVICE AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region. | 01-22-2015 |
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| 20100221726 | RELATING TO DEVICES - A method of analysis, instrument for analysis and device for use in such an instrument are provided, which perform a number of processes need to reach a useful result in the context of a wide variety of samples. The sequence of those processes being optimised. A device, instrument using the device and method of use are also provided which offer reliable performance of a heating based process, with minimal condensation and/or sample loss issues. | 09-02-2010 |
| 20100267092 | COMPONENTS - A method and device structure are provided which enable an archive sample to be collected and detached relative to a device within which a series of processes, such as PCR are being provided. A chamber structure and method of use are provided in which a controlled and precise volume is obtained by control of the relative resistance to flow through various channels. | 10-21-2010 |
| 20110100101 | PERFORMANCE - Instruments, devices and methods of analysis are provided which fully integrate a significant number of process steps in a continuous operation. Accurate positioning and full contact between components is also provided by the relative movement the designs allow. An effect interface between a low cost disposable cartridge or device and the instrument to process it is also detailed. | 05-05-2011 |
| 20130130365 | DEVICES - A method of analysis, instrument for analysis and device for use in such an instrument are provided, which perform a number of processes need to reach a useful result in the context of a wide variety of samples. The sequence of those processes being optimised. A device, instrument using the device and method of use are also provided which offer reliable performance of a heating based process, with minimal condensation and/or sample loss issues. | 05-23-2013 |
| 20130323737 | METHOD AND SYSTEM FOR ANALYZING A SAMPLE - A method and system for analysing a sample are provided, wherein one or more process steps and/or sample processors are provided separately from the instrument, for instance a sample receiving step and sample preparation step and sample extraction step and sample retention step and/or purification step and washing step and elution step, and one or more process steps and/or sample processors provided by the instrument as an integrated set, the one or more process steps and/or sample processors provided by the instrument including a sample receiving step and amplification step and denaturing step and investigation step and detection step and results analysis step and results output step. Other combinations of the split in location of the steps are possible. The optimisation of the split allows the accurate processing by a cartridge based instrument of the sample, whilst fully interfacing with a variety of sample collection and/or preparation approaches. | 12-05-2013 |
| 20140178938 | COMPONENTS - A method and device structure are provided which enable an archive sample to be collected and detached relative to a device within which a series of processes, such as PCR are being provided. A chamber structure and method of use are provided in which a controlled and precise volume is obtained by control of the relative resistance to flow through various channels. | 06-26-2014 |
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| 20090029799 | Golf Clubs and Methods of Manufacture - Embodiments of golf clubs and methods of manufacture are generally described herein. In one embodiment, manufacturing a face plate for a golf club head comprises positioning a label in a mold apparatus, positioning a mold compound over the label and the mold apparatus, and changing the mold compound to a solid form. Other embodiments may be described and claimed. | 01-29-2009 |
| 20090029800 | Golf Clubs and Methods of Manufacture - Embodiments of golf clubs and methods of manufacture are generally described herein. In one embodiment, a golf club head is provided comprising a golf club head housing including a hollow portion having a cavity. A material can be inserted into the cavity to dampen a frequency response of walls of the hollow portion. The golf club head further comprises sight cues to assist a golfer to align the golf club head with a golf ball. Various other embodiments may be described herein and claimed. | 01-29-2009 |
| 20090314399 | Golf Club Head Cover - Embodiments of golf club head covers are described herein. Other embodiments and related examples comprising magnetic elements are also described herein. | 12-24-2009 |
| 20100051151 | Golf Club Head Covers And Related Methods - Embodiments of golf club head covers are described herein. Other embodiments and related examples comprising magnetic elements are also described herein. | 03-04-2010 |
| 20100257721 | Methods For Manufacturing Face Plates For Golf Club Heads - In one embodiment, a method of manufacturing a face plate for a golf club head comprises providing a label for the face plate of the golf club head, providing a mold apparatus, positioning the label in the mold apparatus, providing a mold compound in a non-solid form, positioning the mold compound over the label and in the mold apparatus, and changing the mold compound to a solid form defining the face plate after positioning the mold compound over the label and in the mold apparatus. Other examples, methods, and related apparatuses are disclosed herein. | 10-14-2010 |
| 20120010018 | FACE PLATES FOR GOLF CLUB HEADS AND RELATED METHODS - Embodiments of face plates for golf club heads are disclosed herein. Other examples, and related methods are also disclosed herein. | 01-12-2012 |
| 20120077613 | CLUB HEAD SETS WITH VARYING CHARACTERISTICS AND RELATED METHODS - Embodiments of golf clubs head sets with varying characteristics are disclosed herein. Other examples and related methods are also generally described herein. | 03-29-2012 |
| 20150321056 | GOLF CLUBS WITH ADJUSTABLE LOFT AND LIE AND METHODS OF MANUFACTURING GOLF CLUBS WITH ADJUSTABLE LOFT AND LIE - Embodiments of golf clubs with adjustable loft and lie and methods of manufacturing golf clubs with adjustable loft and lie are generally described herein. Other embodiments may be described and claimed. | 11-12-2015 |
