Patent application number | Description | Published |
20080303166 | TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 12-11-2008 |
20080305306 | SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE - A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process. | 12-11-2008 |
20080305576 | METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL - A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process. | 12-11-2008 |
20080305577 | METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 12-11-2008 |
20090001365 | MEMORY CARD FABRICATED USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 01-01-2009 |
20090001529 | PACKAGE STACKING USING UNBALANCED MOLDED TSOP - A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages. | 01-01-2009 |
20090001533 | MULTI-CHIP PACKAGING IN A TSOP PACKAGE - A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include a leadframe having one or more semiconductor die and one or more passive components affixed thereon. The one or more passive components may be affixed by soldering with a solder material. In embodiments, in order to prevent bleeding of the solder material during a solder reflow process, barricades are formed on the surface of the leadframe, at least partially surrounding the one or more passive components. | 01-01-2009 |
20090001534 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 01-01-2009 |
20090001552 | SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 01-01-2009 |
20090001610 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 01-01-2009 |
20090004774 | METHOD OF MULTI-CHIP PACKAGING IN A TSOP PACKAGE - A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include a leadframe having one or more semiconductor die and one or more passive components affixed thereon. The one or more passive components may be affixed by soldering with a solder material. In embodiments, in order to prevent bleeding of the solder material during a solder reflow process, barricades are formed on the surface of the leadframe, at least partially surrounding the one or more passive components. | 01-01-2009 |
20090004776 | METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 01-01-2009 |
20090004781 | METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 01-01-2009 |
20090004782 | METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 01-01-2009 |
20090004783 | METHOD OF PACKAGE STACKING USING UNBALANCED MOLDED TSOP - A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages. | 01-01-2009 |
20090004785 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 01-01-2009 |
20090065902 | METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECEIVING AN ELECTRICAL CONNECTOR - A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package. | 03-12-2009 |
20090085231 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY PARTICLE BLASTING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. The abrasion process may occur by forcing abrasive particles over the jagged side edges of a semiconductor package as a result of a pressure differential above and below the semiconductor packages. Upon completion of the abrasive process, a second cutting process may be performed which cuts along straight edges and singulates the respective packages from the panel. | 04-02-2009 |
20090256249 | STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages. | 10-15-2009 |
20090263969 | HIDDEN PLATING TRACES - A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided. | 10-22-2009 |
20100055835 | METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA ELECTRICAL CONNECTORS EXTENDING BETWEEN ADJOINING SEMICONDUCTOR PACKAGES - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages. | 03-04-2010 |
20100102440 | HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE - A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die. | 04-29-2010 |
20100289147 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 11-18-2010 |
20110210446 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 09-01-2011 |
20120273968 | Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 11-01-2012 |
20130084677 | METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SDTM card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 04-04-2013 |
20130200507 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 08-08-2013 |