Patent application number | Description | Published |
20080290468 | STRUCTURE OF FLEXIBLE ELECTRONICS AND OPTOELECTRONICS - A method for producing a flexible electronic device is provided. The method comprises steps of providing a flexible substrate, forming an inorganic film on the flexible substrate and etching the inorganic film to obtain an electronic element of the electronic device. In another aspect, a flexible electronic device is provided. The flexible electronic device comprises a flexible substrate and an inorganic film disposed on the flexible substrate and having an electronic element, wherein the electronic element is formed by etching the inorganic film. | 11-27-2008 |
20110032765 | Memory Formed By Using Defects - A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read. | 02-10-2011 |
20110053351 | Solar Cell Defect Passivation Method - The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency. | 03-03-2011 |
20110284074 | PHOTOVOLTAIC CELL - A photovoltaic cell includes a first type doped mono-crystalline silicon substrate, an intrinsic amorphous silicon layer, a second type doped amorphous silicon layer, a first type doped crystalline Ge-containing layer, and a pair of electrodes. The first type doped mono-crystalline silicon substrate has a front surface and a rear surface. The intrinsic amorphous silicon layer is disposed on the front surface. The second type doped amorphous silicon layer is disposed on the intrinsic amorphous silicon layer. The first type doped crystalline Ge-containing layer is disposed on the rear surface. The pair of electrodes are electrically connected to the second type doped amorphous silicon layer and first type doped crystalline Ge-containing layer, respectively. | 11-24-2011 |
20130089943 | METHOD OF MANUFACTURING A SOLAR CELL - An embodiment of the present disclosure provides method of manufacturing a solar cell. The method comprises the steps of providing a silicon substrate, forming a P-N junction structure in the silicon substrate, forming an oxide layer for passivating the surface defect of the substrate that has a low reflectivity for AM1.5G solar spectrum, and forming a plurality of metal electrodes on the silicon substrate. | 04-11-2013 |
20130221534 | Through Silicon Via Layout Pattern - A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape. | 08-29-2013 |
20140124774 | MOSFET DEVICE - A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction. | 05-08-2014 |
20150303299 | 3D UTB TRANSISTOR USING 2D MATERIAL CHANNELS - A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode. | 10-22-2015 |