Chavali
Balatripura S. Chavali, Sugar Land, TX US
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20100088760 | DEBUG SECURITY LOGIC - A system comprises debug logic usable to debug the system. The system also comprises processing logic capable of accessing the debug module using electronic signals. The system further comprises security logic configured to prevent the processing logic from accessing the debug logic unless the security logic is provided with a passkey that matches another passkey stored in the system. | 04-08-2010 |
20120319725 | TESTING FOR MULTIPLEXER LOGIC ASSOCIATED WITH A MULTIPLEXED INPUT/OUTPUT PIN - An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux. | 12-20-2012 |
Balatripura Sodemma Chavali, Sugar Land, TX US
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20120066551 | Run-time Verification of CPU Operation - Safe operation in a processor may be verified by making use of an execution trace module that is normally only used for testing and software development. During operation of the processor in the field, a sequence of instructions may be executed the processor. A portion of the execution is traced to form a sequence of trace data. The sequence of trace data is compressed to form a checksum. The checksum is compared to a reference checksum, and an execution error is indicated when the checksum does not match the reference checksum. | 03-15-2012 |
20140223047 | SYSTEM AND METHOD FOR PER-TASK MEMORY PROTECTION FOR A NON-PROGRAMMABLE BUS MASTER - A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task. | 08-07-2014 |
20140223052 | SYSTEM AND METHOD FOR SLAVE-BASED MEMORY PROTECTION - A system includes a bus slave coupled to a plurality of bus masters via one or more interconnects. The system also includes a memory protection unit (MPU) associated with the bus slave, the MPU having a set of access permissions that grants access to the bus slave from a first bus master and denies access to the bus slave from a second bus master. The MPU generates an error response as result of a transaction generated by a task on the second bus master attempting to access the bus slave. | 08-07-2014 |
20140223127 | SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION - A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented. | 08-07-2014 |
Kameshwar Chavali, Austin, TX US
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20150139249 | System and Method for Debugging - A system and method for debugging an ASIC are described herein. In accordance with this disclosure, a trigger logic unit may trigger a transfer of a multi-bit signal from an internal ASIC state to a compression engine. The compression engine may compress the multi-bit signal to create a compressed signal. A packet engine may packetize the compressed signal for transmission via a debug interface. | 05-21-2015 |
Nanda Kishore Chavali, Attapur IN
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20130077718 | SYSTEM AND METHOD FOR DETECTING A FRAME FORMAT - A method for detecting a format of a frame in a communication system is presented. An embodiment of the method includes receiving the frame comprising a plurality of orthogonal frequency division multiplexing (OFDM) symbols. The plurality of OFDM symbols may include at least one signal field symbol. The method further includes determining a modulation associated with the at least one signal field symbol. The modulation may be a first modulation or a second modulation. Also, the method includes estimating a position of the at least one signal field symbol among the plurality of symbols, and extracting a coding rate of the received frame. The method then includes detecting the format of the received frame based on the determined modulation and the estimated position of the at least one signal field symbol, and the extracted coding rate of the received frame. | 03-28-2013 |
20130136198 | SYSTEM AND METHOD FOR ADAPTIVE TIME SYNCHRONIZATION - A method of estimating a symbol boundary for adaptive time synchronization in a communication system is presented. An embodiment of the method includes receiving a signal comprising a plurality of OFDM symbols from receiver chains. The OFDM symbols include at least a long training field (LTF) symbol. The method further includes determining a normalized correlation signal based on correlation between the received LTF symbol and a reference symbol for each of the receiver chains for different lags. Also, the method includes estimating an energy window length for the normalized correlation signal. The energy window length includes at least one of channel delay spread and a maximum cyclic shift applied to the signal. The method then includes estimating the symbol boundary associated with the received LTF symbol based on a position of peak energy of the normalized correlation signal using the estimated energy window length. | 05-30-2013 |
20140348267 | LOW LATENCY OFDM SYSTEM - A low latency transmitter and receiver for an OFDM system are disclosed. The low latency transmitter includes an FFT module and a baseband modulator. The FFT module computes IDFT of PSK constellation data symbols or QAM constellation data symbols. The baseband modulator performs complex modulation of the IDFT samples by multiplying these samples with 1 and −1 alternatively in time domain. The low latency receiver includes a baseband demodulator and another FFT module. The baseband demodulator performs complex demodulation of the received samples of OFDM symbols by multiplying the samples of OFDM symbols with 1 and −1 alternatively in time domain thereby obtaining baseband demodulated symbols. The FFT module of the receiver computes DFT of samples of the baseband demodulated symbols to obtain samples of the OFDM demodulated symbols. | 11-27-2014 |
Nanda Kishore Chavali, Hyderabad IN
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20140301504 | METHODS AND SYSTEMS FOR REDUCING COMPLEXITY OF MIMO DECODER - Method and system for decomposing a complex channel matrix at MIMO receiver is disclosed. The method comprises determining a real channel matrix from the complex channel matrix, wherein the number of rows and columns of the real channel matrix depends on a number of transmitting chains and a number of receiving chains. Thereafter, the below mentioned steps repeated predetermined number of times: A pre-Householder vector is determined based on the real channel matrix. A Householder vector is determined based on the pre-Householder vector. Thereafter a Householder matrix is determined based on the Householder vector and a transpose of the Householder vector without performing division operation. Finally, an orthogonal matrix and an upper triangular matrix are determined based on the Householder matrix, wherein the upper triangular matrix comprises a predetermined number of zeros in an upper triangle. | 10-09-2014 |
Siva Chavali, Bangalore IN
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20150116911 | ARC DEFLECTING AND VENTILATION ASSEMBLY FOR ELECTRICAL ENCLOSURES AND SYSTEMS FOR ARC DEFLECTING AND VENTILATION - The present invention relates to an arc deflecting and ventilation assembly ( | 04-30-2015 |
Sriram Chavali, Fremont, CA US
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20150319116 | SYSTEM AND METHOD FOR MULTI-CHANNEL DELIVERY OF TRANSFORMED AND AUGMENTED MESSAGES IN REAL-TIME - In a system of interconnected enterprise apps, a business data object maintained by a server undergoes a life cycle event which triggers a message notification. All messages between client applications and the server are intercepted, and a configurable rules engine and message processing filters govern the transformation and delivery of each message according to each recipient's role, application, and login state. Messages can be enhanced by adding contextual information and details from other messages and/or information retrieved from enterprise back-end systems according to the rules. The transformation and delivery of messages occurs in real-time across multiple channels, platforms, and users. | 11-05-2015 |
Srivalli Chavali, Kenmore, WA US
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20140189442 | MESSAGE SERVICE DOWNTIME - The description relates to addressing the downtime of a message service. One example can include determining that an error occurred during a message send process. A decision can be made whether the error is a suspicious error or a non-suspicious error. In an instance where the error is a suspicious error, any resend attempts can be limited to a number of times defined by a crash count threshold. | 07-03-2014 |
20150236821 | MESSAGE SERVICE DOWNTIME - The description relates to addressing the downtime of a message service. One example can include determining that an error occurred during a message send process. A decision can be made whether the error is a suspicious error or a non-suspicious error. In an instance where the error is a suspicious error, any resend attempts can be limited to a number of times defined by a crash count threshold. | 08-20-2015 |
Srivalli Chavali, Redmond, WA US
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20150249683 | MANAGEMENT MODEL FOR MANAGING COMPLIANCE POLICIES - A common set of compliance policy definition user interface displays are displayed and include a common set of user input mechanisms. The user input mechanisms receive user inputs to define a plurality of different types of compliance policies for deployment to a plurality of different workloads. A given compliance policy, defined by the user inputs, is generated for distribution to a given workload. | 09-03-2015 |
Venkata Gautham Chavali, Hyderabad IN
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20150139366 | METHOD AND APPARATUS FOR ENHANCED CHANNEL ESTIMATION USING MATCHING PURSUIT - Apparatus and methods for channel estimation includes determining two streams corresponding to odd and even samples of a received signal that is sampled at a first chip rate, performing least squares successive interference cancellation on each of the two streams to obtain odd and even raw channel estimates, interlacing the odd and even raw channel estimates to obtain interlaced channel estimates, interpolating additional samples in the interlaced channel estimates to create higher chip rate channel estimates, identifying a first set of tap positions based on the higher chip rate channel estimates, and applying matching pursuit to the first set of tap positions to identify a second set of tap positions, wherein the second set of tap positions includes fewer tap positions than the first set of tap positions. | 05-21-2015 |
20150139368 | ENHANCED CHANNEL ESTIMATION IN TD-SCDMA - Apparatus and methods for channel estimation in time division synchronous code division multiple access (TD-SCDMA) based on a signal received from one or more Node Bs include determining least squares channel metric estimates based on the received signal, identifying signal taps and noise taps in a tapped delay line channel estimate based on at least one of temporal correlations of the least squares channel metric estimates or composite hypothesis testing on the least squares channel metric estimates, and updating an interference buffer based on the signal taps and the noise taps. | 05-21-2015 |
Venkata Gautham Chavali, Hyderbad IN
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20150139367 | METHOD AND APPARATUS FOR ENHANCED CHANNEL ESTIMATION USING MATCHING PURSUIT AND ADAPTIVE CLUSTER TRACKING - Apparatus and methods for channel estimation include determining two streams corresponding to odd and even samples of a received signal that is sampled at a first chip rate, performing least squares successive interference cancellation on each of the two streams to obtain odd and even raw channel estimates, interlacing the odd and even raw channel estimates to obtain interlaced channel estimates, interpolating additional samples in the interlaced channel estimates to create higher chip rate channel estimates, identifying a first set of tap positions based on the higher chip rate channel estimates, applying matching pursuit to the first set of tap positions to identify a second set of tap positions, wherein the second set of tap positions includes fewer tap positions than the first set of tap positions, and determining a third set of tap positions by clustering each tap position included in the second set of tap positions. | 05-21-2015 |