Patent application number | Description | Published |
20080303118 | PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSION ZONE - A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter. | 12-11-2008 |
20090091002 | METHODS FOR PRODUCING IMPROVED EPITAXIAL MATERIALS - This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials. | 04-09-2009 |
20090098343 | EPITAXIAL METHODS AND TEMPLATES GROWN BY THE METHODS - This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials. | 04-16-2009 |
20090189185 | EPITAXIAL GROWTH OF RELAXED SILICON GERMANIUM LAYERS - A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 10 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface. | 07-30-2009 |
20090205563 | TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER - The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl | 08-20-2009 |
20090214785 | THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS - The present invention relates to the field of semiconductor processing and provides apparatus and methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the invention comprises heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention comprises radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases. | 08-27-2009 |
20090283029 | ABATEMENT OF REACTION GASES FROM GALLIUM NITRIDE DEPOSITION - Methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment and methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material. | 11-19-2009 |
20100072576 | METHODS AND STRUCTURES FOR ALTERING STRAIN IN III-NITRIDE MATERIALS - Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain. | 03-25-2010 |
20100109126 | METHODS OF FORMING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN, SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING SAME - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 05-06-2010 |
20100124814 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 05-20-2010 |
20100133548 | METHODS FOR IMPROVING THE QUALITY OF EPITAXIALLY-GROWN SEMICONDUCTOR MATERIALS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods. | 06-03-2010 |
20100180913 | METHODS FOR IN-SITU CHAMBER CLEANING PROCESS FOR HIGH VOLUME MANUFACTURE OF SEMICONDUCTOR MATERIALS - The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and apparatus for in-situ removal of undesired deposits in the interiors of reactor chambers, for example, on chamber walls and elsewhere. The invention provides methods according to which cleaning steps are integrated and incorporated into a high-throughput growth process. Preferably, the times when growth should be suspended and cleaning commenced and when cleaning should be terminated and growth resumed are automatically determined based on sensor inputs. The invention also provides reactor chamber systems for the efficient performance of the integrated cleaning/growth methods of this invention. | 07-22-2010 |
20100187568 | EPITAXIAL METHODS AND STRUCTURES FOR FORMING SEMICONDUCTOR MATERIALS - Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming a plurality of substantially strain-relaxed island structures and utilizing such island structures for subsequent further growth of strain-relaxed substantial continuous layers of semiconductor material. | 07-29-2010 |
20100242835 | HIGH VOLUME DELIVERY SYSTEM FOR GALLIUM TRICHLORIDE - The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods and equipment are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the precursor is provided at a mass flow of at least 50 g Group III element/hour for a time of at least 48 hours to facilitate high volume manufacture of the semiconductor material. Advantageously, the mass flow of the gaseous Group III precursor is controlled to deliver the desired amount. | 09-30-2010 |
20100244197 | EPITAXIAL METHODS AND STRUCTURES FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material. | 09-30-2010 |
20100244203 | SEMICONDUCTOR STRUCTURE HAVING A PROTECTIVE LAYER - A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer. | 09-30-2010 |
20100258053 | APPARATUS FOR DELIVERING PRECURSOR GASES TO AN EPITAXIAL GROWTH SUBSTRATE - This invention provides gas injector apparatus that extends into a growth chamber in order to provide more accurate delivery of thermalized precursor gases. The improved injector can distribute heated precursor gases into a growth chamber in flows that spatially separated from each other up until they impinge of a growth substrate and that have volumes adequate for high volume manufacture. Importantly, the improved injector is sized and configured so that it can fit into existing commercial growth chamber without hindering the operation of mechanical and robot substrate handling equipment used with such chambers. This invention is useful for the high volume growth of numerous elemental and compound semiconductors, and particularly useful for the high volume growth of Group III-V compounds and GaN. | 10-14-2010 |
20110011450 | METHODS AND STRUCTURES FOR BONDING ELEMENTS - Embodiments of the invention relate to methods and structures for fabricating semiconductor structures that include at least one bonding layer for attaching two or more elements to one another. The at least one bonding layer may be at least substantially comprised of zinc, silicon and oxygen. | 01-20-2011 |
20110024747 | METHODS FOR IMPROVING THE QUALITY OF GROUP III-NITRIDE MATERIALS AND STRUCTURES PRODUCED BY THE METHODS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods. | 02-03-2011 |
20110037075 | PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSION ZONE - A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter. | 02-17-2011 |
20110057294 | FORMATION OF SUBSTANTIALLY PIT FREE INDIUM GALLIUM NITRIDE - A method of fabricating a device layer structure includes providing a III-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the III-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the III-nitride semiconductor layer. | 03-10-2011 |
20110101373 | METHOD OF FORMING A COMPOSITE LASER SUBSTRATE - A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer ( | 05-05-2011 |
20110156212 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES OR DEVICES USING LAYERS OF SEMICONDUCTOR MATERIAL HAVING SELECTED OR CONTROLLED LATTICE PARAMETERS - Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature. | 06-30-2011 |
20110212546 | UV ABSORPTION BASED MONITOR AND CONTROL OF CHLORIDE GAS STREAM - A semiconductor growth system includes a chamber and a source of electromagnetic radiation. A detector is arranged to detect absorption of radiation from the source by a chloride- based chemical of the reaction chamber. A control system controls the operation of the chamber in response to the absorption of radiation by the chloride-based chemical. The control system controls the operation of the chamber by adjusting a parameter of the reaction chamber. | 09-01-2011 |
20110212603 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 09-01-2011 |
20110277681 | GAS INJECTORS FOR CVD SYSTEMS WITH THE SAME - The present invention provides improved gas injectors for use with chemical vapour deposition (CVD) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates. | 11-17-2011 |
20110284863 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 11-24-2011 |
20110305835 | SYSTEMS AND METHODS FOR A GAS TREATMENT OF A NUMBER OF SUBSTRATES - Systems and methods for the gas treatment of one or more substrates include at least two gas injectors in a reaction chamber, one of which may be movable. The systems may also include a substrate support structure for holding one or more substrates disposed within the reaction chamber. The movable gas injector may be disposed between the substrate support structure and another gas injector. The gas injectors may be configured to discharge different process gasses therefrom. The substrate support structure may be rotatable around an axis of rotation. | 12-15-2011 |
20120085400 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING QUANTUM DOT STRUCTURES AND RELATED STRUCTURES - Methods of fabricating photovoltaic devices include forming a plurality of subcells in a vertically stacked arrangement on the semiconductor material, each of the subcells being formed at a different temperature than an adjacent subcell such that the adjacent subcells have differing effective band-gaps. The methods of fabricating also include inverting the structure, attaching another substrate to the second semiconductor material, and removing the substrate. For example, each of the subcells may comprise a III-nitride material, and each subsequent subcell may include an indium content different than the adjacent subcell. Novel structures may be formed using such methods. | 04-12-2012 |
20120132922 | COMPOSITE SUBSTRATE WITH CRYSTALLINE SEED LAYER AND CARRIER LAYER WITH A COINCIDENT CLEAVAGE PLANE - A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction. | 05-31-2012 |
20120187541 | EPITAXIAL METHODS FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material. | 07-26-2012 |
20120199845 | METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer. | 08-09-2012 |
20120280249 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 11-08-2012 |
20120319128 | SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 12-20-2012 |
20130052806 | DEPOSITION SYSTEMS HAVING ACCESS GATES AT DESIRABLE LOCATIONS, AND RELATED METHODS - Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber. The systems also include at least one access gate through which a workpiece substrate may be loaded into the reaction chamber and unloaded out from the reaction chamber. The at least one access gate is located remote from the gas injection device. Methods of depositing semiconductor material may be performed using such deposition systems. Methods of fabricating such deposition systems may include coupling an access gate to a reaction chamber at a location remote from a gas injection device. | 02-28-2013 |
20130104802 | GALLIUM TRICHLORIDE INJECTION SCHEME | 05-02-2013 |
20130126896 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 05-23-2013 |
20130137247 | THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS - The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases. | 05-30-2013 |
20130161636 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES USING THERMAL SPRAY PROCESSES, AND SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods. | 06-27-2013 |
20130161637 | SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE LAYERS AND OVERLYING SEMICONDUCTOR LAYERS HAVING CLOSELY MATCHING COEFFICIENTS OF THERMAL EXPANSION, AND RELATED METHODS - Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments. | 06-27-2013 |
20130164874 | METHODS OF FORMING DILUTE NITRIDE MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES - Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements. | 06-27-2013 |
20130181308 | METHODS OF FABRICATING DILUTE NITRIDE SEMICONDUCTOR MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES - Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a vapor phase epitaxy (HVPE) chamber. | 07-18-2013 |
20130199441 | GAS INJECTORS FOR CHEMICAL VAPOUR DEPOSITION (CVD) SYSTEMS AND CVD SYSTEMS WITH THE SAME - The present invention provides improved gas injectors for use with CVD (chemical vapour deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates. | 08-08-2013 |
20130221496 | METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer. | 08-29-2013 |
20130234157 | METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS - Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer. | 09-12-2013 |
20130244410 | METHODS OF FORMING BULK III-NITRIDE MATERIALS ON METAL-NITRIDE GROWTH TEMPLATE LAYERS, AND STRUCTURES FORMED BY SUCH METHODS - Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. | 09-19-2013 |
20130285015 | PHOTOACTIVE DEVICES WITH IMPROVED DISTRIBUTION OF CHARGE CARRIERS, AND METHODS OF FORMING SAME - Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure. | 10-31-2013 |
20130327266 | TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER - The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl | 12-12-2013 |
20140041584 | ABATEMENT OF REACTION GASES FROM GALLIUM NITRIDE DEPOSITION - Systems for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment is optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material. | 02-13-2014 |
20140217553 | TEMPLATE LAYERS FOR HETEROEPITAXIAL DEPOSITION OF III NITRIDE SEMICONDUCTOR MATERIALS USING HVPE PROCESSES - Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods. | 08-07-2014 |
20140264265 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
20140264371 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
20140264408 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
20140306320 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES OR DEVICES USING LAYERS OF SEMICONDUCTOR MATERIAL HAVING SELECTED OR CONTROLLED LATTICE PARAMETERS - Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature. | 10-16-2014 |
20140312463 | SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 10-23-2014 |
20140326309 | METHOD FOR PREVENTING AN ELECTRICAL SHORTAGE IN A SEMICONDUCTOR LAYER STACK, THIN SUBSTRATE CPV CELL, AND SOLAR CELL ASSEMBLY - The invention relates to a method for preventing an electrical shortage between at least two layers of a semiconductor layer stack attached by the surface of one of its layers to a substrate via a conductive adhesive by providing an isolating layer on the side walls of the stack or by removing excess material after attaching the stack to the substrate. The invention also relates to a thin substrate CPV cell and to a solar cell assembly. | 11-06-2014 |
20150027519 | MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES - The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate, providing a second substrate having a lower surface and an upper surface, forming at least one first solar cell layer on the first substrate to obtain a first wafer structure, forming at least one second solar cell layer on the upper surface of the second substrate to obtain a second wafer structure, and bonding the first wafer structure to the second wafer structure, wherein the at least one first solar cell layer is bonded to the lower surface of the second substrate and removing the first substrate. | 01-29-2015 |
20150059832 | MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES - The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a final base substrate; providing a first engineered substrate comprising a first zipper layer and a first seed layer; providing a second substrate; transferring the first seed layer to the final base substrate; forming at least one first solar cell layer on the first seed layer after transferring the first seed layer to the final base substrate, thereby obtaining a first wafer structure; forming at least one second solar cell layer on the second substrate, thereby obtaining a second wafer structure; and bonding the first and the second wafer structure to each other. | 03-05-2015 |
20150083202 | MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES - The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first engineered substrate; providing a second substrate; forming at least one first solar cell layer on the first engineered substrate to obtain a first wafer structure; forming at least one second solar cell layer on the second substrate to obtain a second wafer structure; bonding the first wafer structure to the second wafer structure; detaching the first engineered substrate; removing the second substrate; and bonding a third substrate to the at least one first solar cell layer. | 03-26-2015 |