Patent application number | Description | Published |
20080205138 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array. | 08-28-2008 |
20090141561 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved. | 06-04-2009 |
20090290431 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a page buffer circuit. The page buffer circuit includes a memory cell area, a first bit line select unit, and a second bit line select unit. A plurality of memory cells of the memory cell area is connected by bit lines and word lines. The first bit line select unit i s connected to one or more bit lines of the memory cell area and is configured to precharge or discharge a selected bit line in response to a control signal. The second bit line select unit is connected to the same bit line as the first bit line select unit and is configured to precharge or discharge the selected bit line simultaneously with the first bit line select unit. | 11-26-2009 |
20100329005 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines. | 12-30-2010 |
20110157998 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device comprises performing a third program such that threshold voltages of third memory cells, from among memory cells of a selected page, are higher than a third level, after the third program loop is completed, performing a second program loop such that threshold voltages of second memory cells, from among the memory cells, are lower than the third level, but higher than a second level, and after the second program loop is completed, performing a first program loop such that threshold voltages of first memory cells, from among the memory cells, are lower than the second level, but higher than a first level. | 06-30-2011 |
20120099386 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code. | 04-26-2012 |
20120195118 | SEMICONDUCTOR MEMORY APPARATUS, DATA PROGRAMMING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes: a memory unit including a first memory group and a second memory group; and a control unit configured to control input data to be programmed into selected memory cells of the first memory group such that one-bit data is programmed into each of the memory cells of the first memory group when the size of the input data is smaller than a size of data which may be stored into the first memory group during a programming mode, and control the input data programmed in the first memory group to be reprogrammed into selected memory cells of the second memory group during a standby mode after the programming mode, such that multi-bit data are programmed into each of the memory cells of the selected second memory group. | 08-02-2012 |
20130208538 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND DATA SENSING METHOD THEREOF - A nonvolatile semiconductor memory apparatus includes a memory cell block, a plurality of page buffers, and a reference page buffer unit. The memory cell block includes a plurality of memory cell strings each of which includes a plurality of memory cells and a dummy memory cell string which includes a plurality of dummy memory cells. The page buffers sense data stored in the memory cells and apply the sensed data to an output node. The reference page buffer unit senses the dummy memory cells and adjusts the timing to apply the values sensed by the page buffers to the output node. | 08-15-2013 |