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| 20100181500 | METHOD AND SYSTEM FOR LOW TEMPERATURE ION IMPLANTATION - A method comprises pre-cooling a first semiconductor wafer outside of a process chamber, from a temperature at or above 15° C. to a temperature below 5° C. The pre-cooled first wafer is placed inside the process chamber after performing the pre-cooling step. A low-temperature ion implantation is performed on the first wafer after placing the first wafer. | 07-22-2010 |
| 20100240224 | MULTI-ZONE SEMICONDUCTOR FURNACE - A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of heaters arranged and operative to heat the chamber. The heating system includes at least one top heater; at least one bottom heater, and a plurality of sidewall heaters spaced along the height of the reaction chamber to control temperature variations within in the chamber and promote uniform film deposit thickness on the wafers. | 09-23-2010 |
| 20100248496 | ROTATABLE AND TUNABLE HEATERS FOR SEMICONDUCTOR FURNACE - A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers. | 09-30-2010 |
| 20110174991 | SCANNING METHOD AND SYSTEM USING 2-D ION IIMPLANTER - An ion implanter system has a movable wafer support for holding a semiconductor wafer and a beam source that generates a beam for implanting ions in the semiconductor wafer while the wafer is moving. A plurality of path segments are identified, through which the wafer support is to move to expose the semiconductor wafer to the ion beam. A first position and a second position are identified for each respective one of the plurality of path segments, such that, when the wafer is in each first position and each second position, a perimeter of the beam projected in a plane of the wafer is tangent to a perimeter of the wafer. The ion implanter is configured to automatically move the wafer along each of the plurality of path segments, starting at the respective first position on each respective path segment and stopping at the respective second position on the same segment, so as to expose the wafer to the beam for implanting ions in the wafer. | 07-21-2011 |
| 20120009692 | System and Method of Dosage Profile Control - A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation. | 01-12-2012 |
| 20120264296 | METHODS OF FORMING THROUGH SILICON VIA OPENINGS - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 10-18-2012 |
| 20120292629 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process. | 11-22-2012 |
| 20130068162 | System and Method of Dosage Profile Control - A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation. | 03-21-2013 |
| 20130068960 | Apparatus for Monitoring Ion Implantation - An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second sensor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second sensor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer. | 03-21-2013 |
| 20130075623 | MULTI-ION BEAM IMPLANTATION APPARATUS AND METHOD - An multi-ion beam implantation apparatus and method are disclosed. An exemplary apparatus includes an ion beam source that emits at least two ion beams; an ion beam analyzer; and a multi-ion beam angle incidence control system. The ion beam analyzer and the multi-ion beam angle incidence control system are configured to direct the emitted at least two ion beams to a wafer. | 03-28-2013 |
| 20130110276 | MULTI-FACTOR ADVANCED PROCESS CONTROL METHOD AND SYSTEM FOR INTEGRATED CIRCUIT FABRICATION | 05-02-2013 |
| 20130140987 | ION IMPLANTATION WITH CHARGE AND DIRECTION CONTROL - The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode. | 06-06-2013 |
| 20130171746 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-04-2013 |
| 20130264498 | SYSTEM AND METHOD OF ION NEUTRALIZATION WITH MULTIPLE-ZONED PLASMA FLOOD GUN - An apparatus comprises a plasma flood gun for neutralizing a positive charge buildup on a semiconductor wafer during a process of ion implantation using an ion beam. The plasma flood gun comprises more than two arc chambers, wherein each arc chamber is configured to generate and release electrons into the ion beam in a respective zone adjacent to the semiconductor wafer. | 10-10-2013 |
| 20130270454 | SYSTEM AND METHOD OF ION BEAM SOURCE FOR SEMICONDUCTOR ION IMPLANTATION - An apparatus comprises an ionization chamber for providing ions during a process of ion implantation, and an electron beam source device inside the ionization chamber. The electron beam source device comprises a field emission array having a plurality of emitters for generating electrons in vacuum under an electric field. | 10-17-2013 |
| 20130280823 | Apparatus for Monitoring Ion Implantation - An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second senor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second senor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer. | 10-24-2013 |
| 20130295753 | ION BEAM DIMENSION CONTROL FOR ION IMPLANTATION PROCESS AND APPARATUS, AND ADVANCED PROCESS CONTROL - A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate. | 11-07-2013 |
| 20130330938 | ROTATABLE AND TUNABLE HEATERS FOR SEMICONDUCTOR FURNACE - A method for forming a layer of material on a semiconductor wafer using a semiconductor furnace that includes a thermal reaction chamber having a heating system having a plurality of rotatable heaters for providing a heating zone with uniform temperature profile is provided. The method minimizes temperature variations within the thermal reaction chamber and promotes uniform thickness of the film deposited on the wafers. | 12-12-2013 |
| 20140235053 | Methods of Forming Through Silicon Via Openings - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 08-21-2014 |
| 20150083998 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A light-emitting diode (LED) element includes a substrate and a GaN layer formed on the substrate. The GaN layer includes a boundary layer including a surface of the GaN opposing the substrate. The surface has a micro-roughening texture and a macro-roughening texture. The boundary layer includes at least one of As, Si, P, Ge, C, B, F, N, Sb, and Xe ions. | 03-26-2015 |
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| 20100119958 | MASK BLANK, MASK FORMED FROM THE BLANK, AND METHOD OF FORMING A MASK - A mask for manufacturing a semiconductor device comprises a transparent substrate. A metal-containing layer overlies the transparent substrate in a first region. A capping layer overlies and is coextensive with the metal-containing layer without wrapping around side edges of the metal-containing layer. The capping layer is substantially free of nitride. The transparent substrate has a second region separate from the first region. The transparent substrate is exposed in the second region. | 05-13-2010 |
| 20100271612 | METHOD AND PELLICLE MOUNTING APPARATUS FOR REDUCING PELLICLE INDUCED DISTORTION - An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask. | 10-28-2010 |
| 20120207381 | Systems and Methods Eliminating False Defect Detections - A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates. | 08-16-2012 |
| 20120261563 | CONTAMINATION INSPECTION - A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects. | 10-18-2012 |
| 20130323625 | Systems and Methods for Lithography Masks - Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate Mo | 12-05-2013 |
| 20140106262 | Image Mask Film Scheme and Method - A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process. | 04-17-2014 |
| 20140255825 | Mask Blank for Scattering Effect Reduction - Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons. | 09-11-2014 |
| 20140273301 | MOVEABLE AND ADJUSTABLE GAS INJECTORS FOR AN ETCHING CHAMBER - An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity. | 09-18-2014 |
| 20140335446 | Systems and Methods for Lithography Masks - Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate Mo | 11-13-2014 |
| 20150024306 | MASK OVERLAY CONTROL - Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes. | 01-22-2015 |
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| 20090295491 | Carrier Generator - A carrier generator for generating a carrier at a frequency of interest in a wireless communications system comprises an oscillator exhibiting a first impedance, the oscillator comprising an energy storage tank configured to generate a periodic signal, the energy storage tank including at least one inductor and at least one capacitor, and an amplifier coupled with the energy storage tank, the amplifier being configured to amplify an amplitude of the periodic signal, an antenna exhibiting a second impedance smaller than the first impedance, and a network coupled between the oscillator and the antenna, the network including at least one inductor or at least one capacitor and being configured to provide a third impedance such that a resultant impedance of the second impedance and the third impedance as viewed from the oscillator toward the antenna is large enough to facilitate the oscillator to generate the carrier at the frequency of interest. | 12-03-2009 |
| 20130241711 | RADIO-FREQUENCY IDENTIFICATION READER - An RFID reader comprises a memory having a first data for identifying the reader and a second data associated with the first data stored therein; a communication interface; and a microcontroller unit. The microcontroller unit is configured to transmit the first data via the communication interface; receive a first request for transmitting the second data; transmit the second data via the communication interface; receive a third data via the communication interface; overwrite the second data stored in the memory with third data. | 09-19-2013 |
| 20130241716 | TRANSMITTER AND TRANSCEIVER HAVING THE SAME IN AN RFID SYSTEM - A transmitter in an RFID system, the transmitter includes a signal generator which has a PIN diode and generates a first signal, a directional unit connected to a cathode of the PIN diode; and an antenna connected to the directional unit, wherein the signal generator has a first terminal configured to receive a first control signal to control a frequency band of the first signal and a second terminal configured to receive a second control signal to control a modulation depth of the first signal. | 09-19-2013 |
| 20130243120 | ASK MODULATOR AND TRANSMITTER HAVING THE SAME - A modulator which has a first terminal to receive a carrier signal, a second terminal to receive a first control signal to control a frequency band of the carrier signal and a third terminal to receive a second control signal to control a modulation depth of the carrier signal. | 09-19-2013 |
