| Patent application number | Description | Published |
|---|
| 20080201676 | SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS - There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time. | 08-21-2008 |
| 20080209373 | METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS - Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability. | 08-28-2008 |
| 20080209374 | Parameter Ordering For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion. | 08-28-2008 |
| 20080209375 | Variable Threshold System and Method For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. | 08-28-2008 |
| 20080250370 | REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS - An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model. | 10-09-2008 |
| 20080270953 | IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION - Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage. | 10-30-2008 |
| 20080307379 | SYSTEM AND METHOD FOR INCREMENTAL STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS - The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing that is most useful in the inner loop of an automatic computer-aided design (CAD) synthesis or optimization tool. In the statistical re-timing, the delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. | 12-11-2008 |
| 20090013294 | SYSTEM AND METHOD FOR STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS - The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form. | 01-08-2009 |
| 20090094565 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 04-09-2009 |
| 20090100393 | METHOD AND APPARATUS FOR INCREMENTALLY COMPUTING CRITICALITY AND YIELD GRADIENT - In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slack for the circuit, determining a slack of at least one diagnostic entity, and computing a diagnostic metric relating to the diagnostic entity(ies) from the chip slack and the slack of the diagnostic entity(ies). | 04-16-2009 |
| 20090119629 | SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE - A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern. | 05-07-2009 |
| 20090150844 | CRITICAL PATH SELECTION FOR AT-SPEED TEST - A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output. | 06-11-2009 |
| 20090210839 | TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER - A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin. | 08-20-2009 |
| 20090235217 | METHOD TO IDENTIFY TIMING VIOLATIONS OUTSIDE OF MANUFACTURING SPECIFICATION LIMITS - A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range. | 09-17-2009 |
| 20090241078 | METHODS FOR CONSERVING MEMORY IN STATISTICAL STATIC TIMING ANALYSIS - A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis. | 09-24-2009 |
| 20090265674 | METHODS FOR IDENTIFYING FAILING TIMING REQUIREMENTS IN A DIGITAL DESIGN - Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail. | 10-22-2009 |
| 20090288051 | METHODS FOR STATISTICAL SLEW PROPAGATION DURING BLOCK-BASED STATISTICAL STATIC TIMING ANALYSIS - Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data. | 11-19-2009 |
| 20090307645 | METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING - A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis. | 12-10-2009 |
| 20100088658 | METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION - In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed. | 04-08-2010 |
| 20100162064 | METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths. | 06-24-2010 |
| 20100180243 | Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations - A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA). | 07-15-2010 |
| 20100211922 | Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits - A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction. | 08-19-2010 |
| 20100287432 | METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns. | 11-11-2010 |
| 20100293512 | CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT - Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips. | 11-18-2010 |
| 20110191730 | ORDERING OF STATISTICAL CORRELATED QUANTITIES - Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity. | 08-04-2011 |
| 20120047477 | Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis - Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof. | 02-23-2012 |
| 20120117527 | PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS - In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner. | 05-10-2012 |
| 20120124534 | System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times - A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack. | 05-17-2012 |
| 20120191401 | METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns. | 07-26-2012 |
| 20120192136 | ORDERING OF STATISTICAL CORRELATED QUANTITIES - Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity. | 07-26-2012 |
| 20120311514 | Decentralized Dynamically Scheduled Parallel Static Timing Analysis - A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes. | 12-06-2012 |
| 20130018617 | INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGNAANM Buck; Nathan C.AACI UnderhillAAST VTAACO USAAGP Buck; Nathan C. Underhill VT USAANM Dreibelbis; Brian M.AACI UnderhillAAST VTAACO USAAGP Dreibelbis; Brian M. Underhill VT USAANM Dubuque; John P.AACI JerichoAAST VTAACO USAAGP Dubuque; John P. Jericho VT USAANM Foreman; Eric A.AACI FairfaxAAST VTAACO USAAGP Foreman; Eric A. Fairfax VT USAANM Habitz; Peter A.AACI HinesburgAAST VTAACO USAAGP Habitz; Peter A. Hinesburg VT USAANM Hemmett; Jeffrey G.AACI St. GeorgeAAST VTAACO USAAGP Hemmett; Jeffrey G. St. George VT USAANM Venkateswaran; NatesanAACI Hopewell JunctionAAST NYAACO USAAGP Venkateswaran; Natesan Hopewell Junction NY USAANM Visweswariah; ChandramouliAACI Croton-on-HudsonAAST NYAACO USAAGP Visweswariah; Chandramouli Croton-on-Hudson NY USAANM Wang; XiaoyueAACI KanataAACO CAAAGP Wang; Xiaoyue Kanata CAAANM Zolotov; VladmimirAACI Putnam ValleyAAST NYAACO USAAGP Zolotov; Vladmimir Putnam Valley NY US - Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings. | 01-17-2013 |
| 20130031523 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 01-31-2013 |
| 20130036395 | EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS - Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset. | 02-07-2013 |
| 20130104092 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE - In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree. | 04-25-2013 |
| 20130145333 | STATISTICAL CLOCK CYCLE COMPUTATION - Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA. | 06-06-2013 |
| 20130159953 | PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS - In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner. | 06-20-2013 |
| 20130179852 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 07-11-2013 |
| 20140040844 | Method for Achieving An Efficient Statistical Optimization of Integrated Circuits - Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected. | 02-06-2014 |
| 20140096100 | METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS - A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts. | 04-03-2014 |
| 20140115552 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 04-24-2014 |
| 20140123086 | PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form. | 05-01-2014 |
| 20140123089 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 05-01-2014 |
| 20140123091 | HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell. | 05-01-2014 |
| 20140123095 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 05-01-2014 |
| 20140173543 | PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form. | 06-19-2014 |
| 20140298280 | REDUCING RUNTIME AND MEMORY REQUIREMENTS OF STATIC TIMING ANALYSIS - Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis. | 10-02-2014 |
| 20140359547 | HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell. | 12-04-2014 |
| 20150082260 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 03-19-2015 |
