Patent application number | Description | Published |
20090289301 | LASER ANNEALING OF METAL OXIDE SEMICONDUCTORON TEMPERATURE SENSITIVE SUBSTRATE FORMATIONS - A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the temperature sensitive substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device includes at least a layer of metal oxide semiconductor material, an interface of the metal oxide layer with a dielectric layer, and a gate metal layer adjacent the layer of metal oxide semiconductor material and the interface. The method then includes the step of at least partially annealing the layer of metal oxide semiconductor material by heating the adjacent gate metal layer with pulses of infra red or visible light radiation. | 11-26-2009 |
20100012932 | METAL OXIDE TFT WITH IMPROVED CARRIER MOBILITY - A fabrication method is used in conjunction with a semiconductor device having a metal oxide active layer less than 100 nm thick and the upper major surface and the lower major surface have material in abutting engagement to form underlying interfaces and overlying interfaces. The method of fabrication includes controlling interfacial interactions in the underlying interfaces and the overlying interfaces to adjust the carrier density in the adjacent metal oxide by selecting a metal oxide for the metal oxide active layer and by selecting a specific material for the material in abutting engagement. The method also includes one or both steps of controlling interactions in underlying interfaces by surface treatment of an underlying material forming a component of the underlying interface and controlling interactions in overlying interfaces by surface treatment of the metal oxide film performed prior to deposition of material on the metal oxide layer. | 01-21-2010 |
20100019656 | ACTIVE MATRIX ORGANIC LIGHT EMITTING DISPLAY - A full-color active matrix organic light emitting display including a transparent substrate, a color filter positioned on an upper surface of the substrate, a spacer layer formed on the upper surface of the color filter, a metal oxide thin film transistor backpanel formed on the spacer layer and defining an array of pixels, and an array of single color, organic light emitting devices formed on the backpanel and positioned to emit light downwardly through the backpanel, the spacer layer, the color filter, and the substrate in a full-color display. | 01-28-2010 |
20100059742 | STABLE AMORPHOUS METAL OXIDE SEMICONDUCTOR - A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer. | 03-11-2010 |
20100267197 | DOUBLE SELF-ALIGNED METAL OXIDE TFT - A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area. | 10-21-2010 |
20110037054 | AMOLED WITH CASCADED OLED STRUCTURES - An active matrix organic light emitting display includes a plurality of pixels with each pixel including at least one organic light emitting diode circuit. Each diode circuit producing a predetermined amount of light lm in response to power W applied to the circuit and including n organic light emitting diodes cascaded in series so as to increase voltage dropped across the cascaded diodes by the factor of n, where n is an integer greater than one. Each diode of the n organic light emitting diodes produces approximately 1/n of the predetermined amount of light lm so as to reduce current flowing in the diodes by 1/n. The organic light emitting diode circuit of each pixel includes a thin film transistor current driver with the cascaded diodes connected in the source/drain circuit so the current driver provides the current flowing in the diodes. | 02-17-2011 |
20110062431 | LASER ANNEALING OF METAL OXIDE SEMICONDUCTOR ON TEMPERATURE SENSITIVE SUBSTRATE FORMATIONS - A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device includes at least a layer of amorphous metal oxide semiconductor material, an interface of the amorphous metal oxide layer with a dielectric layer, and a gate metal layer adjacent the layer of amorphous metal oxide semiconductor material and the interface. The method then includes the step of at least partially annealing the layer of metal oxide semiconductor material by heating the adjacent gate metal layer with pulses of infra red radiation to improve the mobility and operating stability of the amorphous metal oxide semiconductor material while retaining at least the amorphous metal oxide semiconductor material adjacent the gate metal layer amorphous. | 03-17-2011 |
20110104841 | MASK LEVEL REDUCTION FOR MOFET - A method of fabricating a thin film transistor for an active matrix display using reduced masking operations includes patterning a gate on a substrate. A gate dielectric is formed over the gate and a semiconducting metal oxide is deposited on the gate dielectric. A channel protection layer is patterned on the semiconducting metal oxide overlying the gate to define a channel area and to expose the remaining semiconducting metal oxide. A source/drain metal layer is deposited on the structure and etched through to the channel protection layer above the gate to separate the source/drain metal layer into source and drain terminals and the source/drain metal layer and the semiconducting metal oxide are etched through at the periphery to isolate the transistor. A nonconductive spacer is patterned on the transistor and portions of the surrounding source/drain metal layer. | 05-05-2011 |
20110147761 | TWO-TERMINAL SWITCHING DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points. | 06-23-2011 |
20110227065 | DOUBLE SELF-ALIGNED METAL OXIDE TFT - A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area. | 09-22-2011 |
20110309389 | FULL-COLOR ACTIVE MATRIX ORGANIC LIGHT EMITTING DISPLAY WITH HYBRID - A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band. | 12-22-2011 |
20120104381 | METAL OXIDE TFT WITH IMPROVED STABILITY - A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of low trap density material is sandwiched between the active layer of metal oxide and the layer of gate dielectric. The layer of low trap density material has a major surface parallel and in contact with a major surface of the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide. A second layer of low trap density material can optionally be placed in contact with the opposed major surface of the active layer of metal oxide so that a low trap density interface is formed with both surfaces of the active layer of metal oxide. | 05-03-2012 |
20120168744 | SELF-ALIGNED METAL OXIDE TFT WITH REDUCED NUMBER OF MASKS - A method of fabricating MO TFTs on transparent substrates by positioning opaque gate metal on the front surface of the substrate defining a gate area, depositing gate dielectric material on the front surface of the substrate, overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material on the gate dielectric material. Depositing etch stop material on the semiconductor material. Positioning photoresist on the etch stop material, the etch stop material and the photoresist being selectively removable, and the photoresist defining an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the rear surface of the substrate using the gate metal as a mask and removing exposed portions so as to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material on the etch stop layer and on the semiconductor material to form source and drain areas on opposed sides of the channel area. | 07-05-2012 |
20120182284 | ACTIVE MATRIX FOR DISPLAYS AND METHOD OF FABRICATION - An active matrix incorporated in a color display device includes an array of pixels arranged in n rows and m columns, each pixel having x elements including at least a red, a green, and a blue element. A plurality of m data lines, a different one of the plurality of m data lines being coupled one each to each column of pixels and to each element in each pixel in the column of pixels. A plurality of xn scan lines is provided, the xn scan lines being divided into n groups of x scan lines each. A different group of three xn scan lines is coupled to each row of the n rows of pixels and each of the different x scan lines in each group is coupled to a different one of the x elements. | 07-19-2012 |
20120218241 | DRIVING METHOD FOR IMPROVING STABILITY IN MOTFTs - A method of driving a display device includes providing an array of pixels including rows and columns of pixels, each pixel including a switching/driving transistor circuit and at least one light emitting device. Each row of pixels has a scan line and each column of pixels has a data line. The method further includes defining a frame period during which each pixel in the array of pixels is addressed and dividing the frame period into a write subframe, a display subframe, and a rest subframe. A scan pulse is supplied to each scan line, a data signal to each data line and the light emitting devices are disabled during the write subframe. The light emitting devices are enabled during the display subframe and the switching/driving transistor circuits are disabled. A rest pulse is supplied to all scan lines and the light emitting devices are disabled during the rest subframe. | 08-30-2012 |
20120235138 | MASK LEVEL REDUCTION FOR MOFET - A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode. | 09-20-2012 |
20120300147 | DOUBLE SELF-ALIGNED METAL OXIDE TFT - A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area. | 11-29-2012 |
20120302003 | DOUBLE SELF-ALIGNED METAL OXIDE TFT - A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste. | 11-29-2012 |
20120313092 | METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS - A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal. | 12-13-2012 |
20130032796 | SELF-ALIGNED METAL OXIDE TFT WITH REDUCED NUMBER OF MASKS - A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area. | 02-07-2013 |
20130119396 | TWO-TERMINAL SWITCHING DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points. | 05-16-2013 |
20130143395 | STABLE AMORPHOUS METAL OXIDE SEMICONDUCTOR - A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer. | 06-06-2013 |
20140001462 | HIGH MOBILITY STABILE METAL OXIDE TFT | 01-02-2014 |
20140120640 | LED DIE DISPERSAL IN DISPLAYS AND LIGHT PANELS WITH PRESERVING NEIGHBORING RELATIONSHIP - A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship. | 05-01-2014 |
20140138673 | SELF-ALIGNED METAL OXIDE TFT WITH REDUCED NUMBER OF MASKS AND WITH REDUCED POWER CONSUMPTION - A method of fabricating MOTFTs includes positioning opaque gate metal on a transparent substrate, depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Etch stop material is deposited on the semiconductor material. Photoresist defines an isolation area in the semiconductor material. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas. | 05-22-2014 |
20140151694 | METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS - A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal. | 06-05-2014 |
20140167046 | PIXELATED IMAGER WITH MOTFET AND PROCESS - A method of fabricating a pixelated imager includes providing a substrate with bottom contact layer and sensing element blanket layers on the contact layer. The blanket layers are separated into an array of sensing elements by trenches isolating adjacent sensing elements. A sensing element electrode is formed adjacent each sensing element overlying a trench and defining a TFT. A layer of metal oxide semiconductor (MOS) material is formed on a dielectric layer overlying the electrodes and on an exposed upper surface of the blanket layers defining the sensing element adjacent each TFT. A layer of metal is deposited on each TFT and separated into source/drain electrodes on opposite sides of the sensing element electrode. The metal forming one of the S/D electrodes contacts the MOS material overlying the exposed surface of the semiconductor layer, whereby each sensing element in the array is electrically connected to the adjacent TFT by the MOS material. | 06-19-2014 |
20140167047 | METAL OXIDE TFT WITH IMPROVED TEMPERATURE STABILITY - A metal oxide thin film transistor includes a metal oxide semiconductor channel with the metal oxide semiconductor having a conduction band with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band with a second energy level equal to, or less than 0.5 eV above the first energy level. | 06-19-2014 |
20140273319 | FULL-COLOR ACTIVE MATRIX ORGANIC LIGHT EMITTING DISPLAY WITH HYBRID - A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band. | 09-18-2014 |
20140346495 | STABLE HIGH MOBILITY MOTFT AND FABRICATION AT LOW TEMPERATURE - A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm | 11-27-2014 |
20150014627 | TWO-TERMINAL ELECTRONIC DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV. | 01-15-2015 |