Patent application number | Description | Published |
20140125537 | Feed Horn - A feed horn for a Low Noise Block down converter is disclosed. The feed horn includes a conical body for gathering satellite signals and a connector coupled to the conical body for coupling the feed horn to a waveguide of the Low Noise Block down converter to transmit the satellite signals to the waveguide. The conical body includes a plurality of corrugations, one of the plurality of corrugations includes a plurality of first openings, and a plurality of second openings, each of the plurality of second openings is formed between the two adjacent first openings, wherein the plurality of first openings and the plurality of second openings are used as slits to induce an interference effect to adjust a beam pattern of the feed horn. | 05-08-2014 |
20150091771 | Feeding Apparatus and Low Noise Block Down-converter - A feeding apparatus includes a substrate, an annular grounded metal sheet having a first opening and a second opening, a rectangular grounded metal sheet extending from the annular grounded metal sheet toward an interior according to a configuration of a septum polarizer of a waveguide, a first parasitic grounded metal sheet extending from a side of the rectangular grounded metal sheet along a first direction, a second parasitic grounded metal sheet extending from another side of the rectangular grounded metal sheet along a second direction, a first feeding metal sheet extending from the first opening toward the interior and including a first portion, a second portion and a third portion and a second feeding metal sheet extending from the second opening toward the interior and including a fourth portion, a fifth portion and a sixth portion. | 04-02-2015 |
Patent application number | Description | Published |
20110148371 | SWITCHED-MODE POWER SUPPLY - A switched-mode power supply (SMPS) uses an equivalent inductor of bonding wire(s) and lead frame(s) to replace a traditional external inductor. A current-controlled pulse width modulation (PWM) modulator and a current-controlled pulse frequency modulation (PFM) modulator are optionally employed for high frequency switching, so as to mate a low inductance value of the bonding wire(s) and lead frame(s) and achieve reduced cost, low power consumption and low complexity. | 06-23-2011 |
20120274394 | CHARGE PUMP FEEDBACK CONTROL DEVICE AND METHOD USING THE SAME - Charge pump feedback control device and method are provided. The device is coupled to the charge pump unit which receives an input voltage so as to generate an output voltage and has switches and at least one capacitor, the device includes: a compensation unit, a modulation unit, and a phase control unit. The compensation unit receives the output voltage, compensates the output voltage for stability, and generates an error signal. The modulation unit receives the error signal, modulates the error signal, and correspondingly generates a modulation signal. The phase control unit receives the modulation signal so as to generate phase signal, and controls the plurality of switches of the charge pump unit according to the plurality of phase signal so as to generate the output voltage through the input voltage charging/discharging at least one capacitor of the charge pump unit. | 11-01-2012 |
20130162229 | CHARGE PUMP FEEDBACK CONTROL DEVICE AND METHOD USING THE SAME - Charge pump feedback control device and method are provided. The device is coupled to the charge pump unit which receives an input voltage so as to generate an output voltage and has switches and at least one capacitor, the device includes: a compensation unit, a modulation unit, and a phase control unit. The compensation unit receives the output voltage, compensates the output voltage for stability, and generates an error signal. The modulation unit receives the error signal, modulates the error signal, and correspondingly generates a modulation signal. The phase control unit receives the modulation signal so as to generate phase signal, and controls the plurality of switches of the charge pump unit according to the plurality of phase signal so as to generate the output voltage through the input voltage charging/discharging at least one capacitor of the charge pump unit. | 06-27-2013 |
Patent application number | Description | Published |
20090055574 | NAND Flash Memory Device And Related Method Thereof - The NAND flash memory device contains a NAND flash memory, a mirror data area, and a controller. The mirror data area has a size at least to hold a page of data and is usually formed by random access memory. The controller saves a data to be written into the NAND flash memory that occupies a partial number of the sectors of a first page of the NAND flash memory into the sectors of a second page of the mirror data area. When a new data is to be written into the remaining sectors of the first page of the NAND flash memory, the new data is stored instead into the second page's remaining sectors of the mirror data area. When the second page of the mirror data area is full, the entire second page is written into the first page of the NAND flash memory. | 02-26-2009 |
20090100214 | Management Platform For Extending Lifespan Of Memory In Storage Devices - A management platform for extending lifespan of memory, such as SD, MMC, micro SD, of storage devices is provided. The memory includes a plurality of virtual access units, and a virtual block is defined to include a fixed number of virtual access units. In the management platform, a memory control unit tallies the number of operations performed on a virtual access unit when the virtual access unit is selected to perform on. A processing unit determines whether the data stored in virtual access units should be move to another virtual access unit according to an operation threshold in order to prevent from data loss caused by the memory damage. | 04-16-2009 |
20090114722 | Card Reader With Capability Of Adjusting Access Interface Display - A card reader with capability of adjusting the access interface display is provided, including a connection interface for electrically connecting to the host, a plurality of access interfaces for electrically connecting to corresponding memory cards, such as SD, CF, and a controller. When the host completes the enumeration, the controller issues a disconnect signal through the connection interface to the host to erase the original disk mappings, such as G:, F:, on the display for subsequent adjustment. For adjusting the display, the controller issues an optional reconnect signal belonging to the card reader to the host so that the host can execute the re-enumeration and adjust the displaying of the access interface available in the card reader according to the optional reconnect signal. | 05-07-2009 |
20090157999 | Control Mechanism For Multi-Functional Chips - A control mechanism for multi-functional chips is provided. By receiving operation signals from the predefined pins of the different operation functions, the present invention accesses the corresponding storage area in the memory module according to the operation signals without using different memory modules and memory controllers corresponding to different operation functions so as to save power and reduce the hardware size. For example, the MegaSIM™ multi-functional chip includes the integration of a plurality of operation functions, such as SD/MMC and ISO 7816. Each operation function uses different communication protocol to provide operation signals through individual to shared predefined pins. For example, MegaSIM™ I/O, Vpp/CLK, GND, CLK RST, and Vcc pins are used by ISO 7816, and Cmd, Data0, and Vpp/CLK pins are used by SD/MMC. | 06-18-2009 |
20100122014 | Method For Protecting Memory Proprietary Commands - A method for protecting memory proprietary command is provided. By using the logic block area (LBA) address in the header of the LBA mode, the device end can determine whether the data sector in the LBA mode includes a proprietary command. Also, by using the pre-defined computation function to establish a relation among the values stored in a plurality of characteristic point addresses and a specific point address so that he device end can determine whether a proprietary command is received. As the operating system will not filter out the proprietary command wrapped in this manner, the proprietary command can pass the operating system and be executed by the device end. | 05-13-2010 |
20100131808 | Method For Testing Memory - A memory testing method is provided, by using the computation capability of a controller to receive the testing command the program code of a testing PC to generate random data or use an algorithm to generate testing data of specific format. Then, the method writes the data directly to the flash memory and read the data from the memory again to compare with the original data. The comparison result is transmitted back to the testing PC. The method greatly reduces the memory access frequency and I/O load of the testing PC so as to improve the testing efficiency. | 05-27-2010 |
20100146221 | Method For Protecting Memory Data - A method for protecting memory data is provided, by extracting bad block addresses stored in the bad block information obtained during the memory scanning testing as memory label, and using an algorithm to compute an identification based on the memory label so that the memory will check the identification and whether the blocks pointed by memory label being bad blocks when an external device request data reading so as to prevent the unauthorized data from being read and achieve the object of protecting memory data. | 06-10-2010 |
Patent application number | Description | Published |
20150032918 | MULTIPLE-FORMAT MULTIMEDIA INTERFACE MODULE - The present invention is a multiple-format multimedia interface module, comprising a first port, a circuit module, a first transmission line, a second port, and a second transmission line. The multiple-format multimedia interface module connects a mobile device with a display device conveniently, and may bidirectionally transmit signals between a transmitter end with multiple signal formats of MHL, MyDP, and USB and a receiver end with a single signal format of HDMI or bidirectionally transmit signals between a transmitter end with a single signal format and a receiver end with multiple signal formats. | 01-29-2015 |
20150035579 | LOW-RIPPLE POWER SUPPLY - The present invention is a low-ripple power supply comprising a clock generator, a plurality of charge pump modules, and an adder unit. The low-ripple power supply inputs each of a plurality of clock signals generated by the clock generator into each of the plurality of charge pump modules. Since each of the plurality of charge pump modules sends the inputted corresponding clock signal into two paths to be inputted into the first and the second charge pump, respectively, and the corresponding clock signal inputted into the second charge pump undergoes an inversion by the inverter, by adding the first voltage outputted by the first charge pump and the second voltage outputted by the second charge pump, the ripples may be eliminated; finally, the adder unit adds the voltages outputted by each of the plurality of charge pump modules to yield a low-ripple DC voltage. | 02-05-2015 |
Patent application number | Description | Published |
20090038924 | AUTOMATIC TIMING SWITCH DEVICE - An automatic timing switch device includes a switch control wheel, a driving assembly, and a plurality of push switches. The switch control wheel includes a plurality of wheel-shaped structures stacked sequentially, wherein each of the wheel-shaped structures has at least one notch formed on an outer periphery of the switch control wheel, and the diameters of the wheel-shaped structures reduce sequentially so that the switch control wheel is in tapered shape. The driving assembly drives the switch control wheel to rotate. The push switches are switched by engaging into or separating from the notches of the wheel-shaped structures as the switch control wheel rotated by the driving assembly. Since the switch control wheel is in a tapered shape, so that the switch control wheel is easily to be formed monolithically and is convenient to be installed to the case of the automatic timing switch device. | 02-12-2009 |
20090046540 | AUTOMATIC TIMING CONTROL DEVICE CASE - An automatic timing control device case which is used for accommodating a timing control rotation shaft and a plurality of switches. A motor is disposed on the case for driving a gear set connected to the timing control rotation shaft to rotate, thereby controlling on or off of the switches through the timing control rotation shaft. The automatic timing control device case includes a body and a gear box. The body has an accommodation space for accommodating the timing control rotation shaft and the plurality of switches. The gear box is integrally formed in the body for accommodating the gear set. The gear box has at least one through-hole communicating the gear box and the accommodation space, such that the gear set is connected to and drives the timing control rotation shaft. | 02-19-2009 |
20110186412 | TIMER - A timer includes a case, a shaft, a cam wheel, a drive mechanism, and a plurality of switch blades disposed within the case. The shaft is rotatably and reciprocally movably disposed in the case. The cam wheel is pivoted on the shaft and rotates together with the shaft when setting, or rotates independently by the drive mechanism. The cam wheel includes a plurality of cam tracks on one side surface thereof and a plurality of ratchets and grooves on a circular rim thereof. The drive mechanism contacts the ratchets to drive the cam wheel to rotate relative to the shaft. The switch blades respectively contact the cam tracks of the cam wheel, and correspondingly generate an electrical connection/disconnection. When the shaft moves to the setting position and the cam wheel being rotated by the user, a flexible element touches the grooves formed on the circular rim results a tactile feedback. | 08-04-2011 |
Patent application number | Description | Published |
20120025258 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE - An exemplary LED module includes a board and an LED package mounted on the plate. The LED package includes a base, an LED chip mounted on a top surface of the base, two electrodes formed on the base and electrically connected to the LED chip and the board, and an encapsulant encapsulating the LED chip. A plurality of grooves are defined in the bottom surface of the base. When the LED package is secured on the plate via solder paste, the grooves function as a container for receiving excessive solder paste, thereby preventing the solder paste from spilling and floating or inclination of the LED package. | 02-02-2012 |
20120080696 | LIGHT EMITTING DIODE MODULE - An LED module includes a plurality of lighting sources each including a substrate, a first and second lead frames arranged on the substrate, an LED chip electrically connected to the first and the second lead frames, and an encapsulation covering the LED chip. The first lead frame of each of the lighting sources connects with the second lead frame of an adjacent lighting source electrically and mechanically. | 04-05-2012 |
20120091485 | LIGHT EMITTING DEVICE - A light emitting diode device comprises a light source and a gas vent device. The gas vent device comprises a base having a collector, wherein a conversion element is located inside the collector. A portion of heat generated from the light source is transferred into thermal energy to gasify the conversion element and the other portion is dissipated via the gas vent device. Therefore, the light emitting device is able to provide illuminant and gasify the conversion element simultaneously. | 04-19-2012 |
20120091487 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode package comprises a substrate and a lens. The substrate comprises two electrodes and a LED chip disposed thereon, wherein the LED chip electrically connects to one of the electrodes via a conductive wire. The connection between the conductive wire and the corresponding electrode is covered by an encapsulation. The lens is located on the substrate and covers the encapsulation. Moreover, the substrate comprises at least two tunnels inside the covering of the lens penetrating the substrate. A collector is located between the substrate and the lens, wherein a transparent layer is formed inside the collector by injecting fluid material through the tunnels or directly injecting fluid material into the collector. A method for manufacturing the light emitting diode package is also provided. | 04-19-2012 |
20120107975 | METHOD FOR PACKAGING LIGHT EMITTING DIODE - An LED packaging method includes: providing a mold with two isolated receiving spaces and a substrate with a die supporting portion and an electrode portion respectively received in the two receiving spaces; disposing an LED die on the die supporting portion and electrically connecting the LED die to the electrode portion of the substrate by metal wires; injecting a light wavelength converting material into the first receiving space and covering the LED die with the light wavelength converting material; communicating the first receiving space to the second receiving space, injecting a first light transmissive material into the communicated first and second spaces, and covering the light wavelength converting material and the metal wires with the first light transmissive material; and removing the mold to obtain a packaged LED. | 05-03-2012 |
20130062650 | LED PACKAGE AND MOLD OF MANUFACTURING THE SAME - The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package. | 03-14-2013 |
20140051195 | METHOD OF MANUFACTURING ENCAPSULATION STRUCTURE FOR ENCAPSULATING LED CHIP - A method of manufacturing an encapsulation structure for encapsulating an LED chip includes the following steps: providing a first encapsulation defining a receiving room for receiving the LED chip therein and a second encapsulation defining a receiving space for receiving the first encapsulation therein; providing a mounting tablet defining an entrance therein, mounting the first encapsulation and the second encapsulation on the mounting tablet with a clearance defined therebetween communicating with the entrance; injecting a liquid transparent resin with phosphorous compounds disturbed therein into the clearance via the entrance; and solidifying the liquid transparent resin to form a transparent resin layer interconnecting the first encapsulation and the second encapsulation. | 02-20-2014 |
20140134766 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE PACKAGE - A method of manufacturing a light emitting device package, includes following steps: providing a base which having a first surface and an opposite second surface, and electrical structures formed on the first surface, defining two through holes through the first and second surfaces; mounting a light emitting element on the first surface, the light emitting element having one pad on a top surface thereof; forming a mask on the first surface, the mask covering the light emitting element and defining at least one opening for exposing the at least one pad; electrically connecting the at least one pad to the electrical structures via at least one metal wire; filling liquid encapsulating material in a space between the mask and the first surface to form an encapsulating layer that encapsulating the light emitting element, the encapsulating layer being separated from the at least one metal wire and comprising phosphors therein. | 05-15-2014 |
Patent application number | Description | Published |
20090086142 | LIQUID CRYSTAL DISPLAY PANEL AND ARRAY SUBSTRATE THEREOF - A liquid crystal display panel includes an array substrate, an opposite substrate having an opposite electrode, a liquid crystal layer located therebetween, first alignment patterns and second alignment patterns. The array substrate includes scan lines, data lines and pixel units electrically connecting corresponding scan lines and data lines. Each pixel unit includes a first active device, a first pixel electrode electrically connecting the first active device and a second pixel electrode. The first pixel electrode and the second pixel electrode are separated to define a first displaying region and a second displaying region. The extending directions of the first alignment patterns in the first displaying region and the second alignment patterns in the second displaying region respectively intersect the extending direction of the scan lines at a smaller first acute angle and a greater acute angle for controlling the arrangements of the liquid crystal molecules. | 04-02-2009 |
20090086144 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel including a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a second substrate, and a liquid crystal layer is provided. The scan lines, data lines, and pixel structures are disposed on the first substrate. The pixel structures are electrically connected to the corresponding scan lines and data lines. The liquid crystal layer is disposed between the first and the second substrates. Each pixel structure includes a first active device, a first pixel electrode electrically connected to the first active device, and a second pixel electrode. A V-shaped main slit formed between the first and the second pixel electrodes has a tip and two branches connected thereto. The tip of the V-shaped main slit directs towards the second pixel electrode. The edges of the first and the second pixel electrodes adjoining each branch are substantially parallel. | 04-02-2009 |
20100091232 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel including a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a second substrate, and a liquid crystal layer is provided. The scan lines, data lines, and pixel structures are disposed on the first substrate. The pixel structures are electrically connected to the corresponding scan lines and data lines. The liquid crystal layer is disposed between the first and the second substrates. Each pixel structure includes a first active device, a first pixel electrode electrically connected to the first active device, and a second pixel electrode. A V-shaped main slit formed between the first and the second pixel electrodes has a tip and two branches connected thereto. The tip of the V-shaped main slit directs towards the second pixel electrode. The edges of the first and the second pixel electrodes adjoining each branch are substantially parallel. | 04-15-2010 |
Patent application number | Description | Published |
20120025278 | SCHOTTKY DIODE - A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced. | 02-02-2012 |
20120126323 | SEMICONDUCTOR DEVICE HAVING A SPLIT GATE AND A SUPER-JUNCTION STRUCTURE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region. | 05-24-2012 |
20120211832 | SPLIT-GTE LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVISE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure. | 08-23-2012 |
20130277718 | JFET DEVICE AND METHOD OF MANUFACTURING THE SAME - A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer. | 10-24-2013 |
20150179631 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region. | 06-25-2015 |
20150325694 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF OPERATING THE SAME - Provided is a semiconductor device including a metal oxide semiconductor transistor, a Zener diode, and a resistor. The metal oxide semiconductor transistor includes a gate, a source and a drain. The resistor has one end electrically connected to the drain, wherein the resistor includes a high resistance which is sufficient for flowing most of current to pass the metal oxide semiconductor transistor. The Zener diode includes a cathode and an anode, in which the cathode is electrically connected the gate and another end of the resistor, and the anode is electrically connected to a gate body. | 11-12-2015 |
Patent application number | Description | Published |
20140145222 | LED Array - An LED array includes: a first LED unit having a first active layer and a first side; a second LED unit having a second active layer and a second side facing the first side; a trench separating the first LED unit from the second LED unit; and a light-guiding structure formed between the first LED unit and the second LED unite for guiding the light emitted by the first active layer and the second active layer away from the LED array. | 05-29-2014 |
20150060924 | OPTOELECTRONIC DEVICE AND THE MANUFACTURING METHOD THEREOF - An optoelectronic device comprises a semiconductor stack having a first surface, a contact layer having a first pattern on the first surface for ohmically contacting the semiconductor stack, a void in the semiconductor stack and surrounding the contact layer, and a mirror structure on the first surface and covering the contact layer, wherein the first surface has a first portion which is not covered by the contact layer and a second portion covered by the contact layer, and the first portion is rougher than the second portion. | 03-05-2015 |
20150144984 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device comprises a semiconductor stack comprising a side, a first surface and a second surface opposite to the first surface, wherein the semiconductor stack further comprises a conductive via extending from the first surface to the second surface; a transparent conductive layer formed on the second surface; a first pad portion and a second pad portion formed on the first surface and electrically connected to the semiconductor stack; and an insulating layer formed between the first pad portion and the semiconductor stack and between the second pad portion and the semiconductor stack. | 05-28-2015 |
20160005941 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes a periphery surface surrounding the active layer; a plurality of vias penetrating the semiconductor stack to expose the first semiconductor layer; and a patterned metal layer formed on the plurality of vias and covered the periphery surface of the first semiconductor layer. | 01-07-2016 |