Patent application number | Description | Published |
20120001272 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULE AND ELECTRONIC SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a cell area and a peripheral area, the cell area having an active region defined by an isolation region, a cell gate structure below an upper surface of the substrate in the cell area, the cell gate crossing the active region, a bit line structure above an upper surface of the substrate in the cell area, the bit line structure including bit line offset spacers on at least two side surfaces thereof, and a peripheral gate structure above an upper surface of the substrate in the peripheral area, the peripheral gate structure including peripheral gate offset spacers and peripheral gate spacers on at least two side surfaces thereof. | 01-05-2012 |
20140206186 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer. | 07-24-2014 |
20140231892 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern. | 08-21-2014 |
20140264953 | WIRING STRUCTURES, METHODS OF MANUFACTURING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING THE SAME - A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer. | 09-18-2014 |