| Patent application number | Description | Published |
|---|
| 20080222400 | Power Consumption of a Microprocessor Employing Speculative Performance Counting - Reduction of power consumption and chip area of a microprocessor employing speculative performance counting, comprising splitting a counter and a backup register of a speculative counting mechanism performing the speculative performance counting into first and second parts each, re-using an available storage within the microprocessor as first parts respectively; integrating at least one dedicated pre-counter into the microprocessor as second parts respectively; splitting the data handled by the speculative counting mechanism in high-order and low-order bits; storing the high order bits in the first parts; storing the low order bits in the second parts; updating the first parts periodically; and saving and propagating the carry-out from the second parts to high-order bits when a corresponding first part of the second parts is next updated respectively. | 09-11-2008 |
| 20080270860 | Integrated Circuit for Writing and Reading Registers Distributed Across a Semiconductor Chip - An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring. | 10-30-2008 |
| 20080276140 | SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP - A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains. | 11-06-2008 |
| 20090021288 | Signal Delay Element, Method and Integrated Circuit Device for Frequency Adjustment of Electronic Signals - The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal. | 01-22-2009 |
| 20090172615 | METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION - The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L | 07-02-2009 |
| 20100013446 | METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT - The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module ( | 01-21-2010 |
| 20120218031 | METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT - The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module ( | 08-30-2012 |
| 20130113545 | METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT - The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module ( | 05-09-2013 |
| 20130145188 | Advanced Pstate Structure with Frequency Computation - A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity. | 06-06-2013 |
| 20140344823 | INTERRUPTION OF CHIP COMPONENT MANAGING TASKS - Embodiments include an apparatus comprising a processor and a computer readable storage medium having computer usable program code. The computer usable program code can be configured to determine whether priority of a requested task is higher than a priority of a currently executing task. The computer usable program code can be further configured to determine whether a value indicates that the currently executing task can be interrupted. The computer usable program code can be configured to trigger execution of the requested task on the processor, if the value indicates that the currently executed task can be interrupted. The computer usable program code can be further configured to wait for lapse of a time period and, interrupt the currently executing task upon detection of lapse of the time period or detection of a change to the value, if the value indicates that the currently executing task cannot be interrupted. | 11-20-2014 |
| 20140344824 | INTERRUPTION OF CHIP COMPONENT MANAGING TASKS - Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted. | 11-20-2014 |
| 20150089311 | CHIP TESTING WITH EXCLUSIVE OR - A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel. | 03-26-2015 |
| 20150089312 | CHIP TESTING WITH EXCLUSIVE OR - A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel. | 03-26-2015 |
