Patent application number | Description | Published |
20100067282 | MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS - The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage. | 03-18-2010 |
20100117121 | MIRRORED-GATE CELL FOR NON-VOLATILE MEMORY - A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate. | 05-13-2010 |
20100232211 | MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS - The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage. | 09-16-2010 |
20110194330 | MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS - The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage. | 08-11-2011 |
20120037875 | MIRRORED-GATE CELL FOR NON-VOLATILE MEMORY - A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate. | 02-16-2012 |
Patent application number | Description | Published |
20100110756 | VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 05-06-2010 |
20110026307 | VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 02-03-2011 |
20110058404 | VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 03-10-2011 |
20110156115 | APPARATUS FOR VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 06-30-2011 |
20120230084 | APPARATUS FOR VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 09-13-2012 |
Patent application number | Description | Published |
20120225301 | OPTICAL DEVICE WITH ANTISTATIC COATING - Optical devices comprising at least one optical layer and at least one antistatic layer disposed on at least one surface of the optical layer wherein the antistatic layer comprises the reaction product of: (a) at least one polymerizable onium salt; and (b) at least one polymerizable, non-onium, silicone or perfluoropolyether moiety-containing monomer, oligomer, or polymer. | 09-06-2012 |
20120288675 | OPTICAL DEVICE WITH ANTISTATIC PROPERTY - An optical device having a first optical member, a second optical member, and an antistatic layer disposed between the first optical member and the second optical member wherein the antistatic layer contains the reaction product of a mixture comprising at least one polymerizable onium salt having an anion and at least one non-onium polymerizable monomer, oligomer, or polymer. | 11-15-2012 |
20140016208 | OPTICAL STACK COMPRISING ADHESIVE - Presently described are optical stacks comprising a first optical film comprising a plurality of structures comprising an optically active portion designed primarily to provide optical gain and optionally an optically in-active bonding portion disposed on a first surface bonded to a second optical film with a light-transmissive adhesive layer such that a portion of the structures penetrate the adhesive layer and a separation is provided between the adhesive layer and the first surface. In one embodiment, the optical stacks exhibit a combination of high peel strength and high retained brightness, particularly after aging. The adhesive layer preferably comprises an interpenetrating network of the reaction product of a polyacrylate component and a polymerizable monomer and the adhesive layer has an elastic modulus ranging from 100 to 2000 MPa at 25° C. | 01-16-2014 |