Patent application number | Description | Published |
20080303061 | Substrate Production Method and Substrate - A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method. | 12-11-2008 |
20090014720 | METHOD OF TREATING INTERFACE DEFECTS IN A SUBSTRATE - The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate. | 01-15-2009 |
20090321829 | LOW-COST DOUBLE-STRUCTURE SUBSTRATES AND METHODS FOR THEIR MANUFACTURE - In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates. | 12-31-2009 |
20090321872 | LOW COST SUBSTRATES AND METHOD OF FORMING SUCH SUBSTRATES - In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate. | 12-31-2009 |
20090321873 | LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE - In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates. | 12-31-2009 |
20100032805 | METHODS AND STRUCTURES FOR RELAXATION OF STRAINED LAYERS - The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that the reflow of the first and the second low-viscosity layers permits the strained-material layer to at least partly relax. | 02-11-2010 |
20110012200 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-20-2011 |
20110042780 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES OBTAINED BY SUCH METHODS - In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate. | 02-24-2011 |
20110133776 | ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures. | 06-09-2011 |
20110133822 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures. | 06-09-2011 |
20110134690 | METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER - The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a front control gate being arranged on top of the channel and separated from the latter by a gate dielectric and a back control gate being arranged in the base substrate and separated from the channel by the insulating layer (BOX). In a cell programming operation, the front control gate and the back control gate are operated jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, with the first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate. | 06-09-2011 |
20110134698 | FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER - The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays. | 06-09-2011 |
20110143522 | RELAXATION OF STRAINED LAYERS - The present invention relates to a method for relaxing a strained material layer by depositing a first low-viscosity layer on a first face of a strained-material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained-material layer; and applying a mechanical pressure to a second face of the strained material layer which is opposite to the first face. The mechanical pressure is applied perpendicularly to the strained material layer during at least part of the heat treatment. | 06-16-2011 |
20110169087 | MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER - The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells. | 07-14-2011 |
20110169090 | DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BURIED INSULATING LAYER, AND PROCESS FOR FABRICATING SAID DEVICE - The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices. | 07-14-2011 |
20110170327 | DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY - The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention. | 07-14-2011 |
20110170343 | DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR - The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells. | 07-14-2011 |
20110215860 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells. | 09-08-2011 |
20110222361 | NANO-SENSE AMPLIFIER - A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. | 09-15-2011 |
20110233675 | SRAM-TYPE MEMORY CELL - An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation. | 09-29-2011 |
20110241157 | METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound. | 10-06-2011 |
20110242926 | PSEUDO-INVERTER CIRCUIT ON SeO1 - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 10-06-2011 |
20110260233 | DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR - The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers. | 10-27-2011 |
20110287571 | METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR - A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality. | 11-24-2011 |
20110294277 | METHODS FOR MANUFACTURING MULTILAYER WAFERS WITH TRENCH STRUCTURES - The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like. | 12-01-2011 |
20120181609 | FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER - The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer. | 07-19-2012 |
20120214291 | RELAXATION OF STRAINED LAYERS - A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material. | 08-23-2012 |
20120231606 | MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES - The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing. | 09-13-2012 |
20120243360 | SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED WITH A LOCAL COLUMN DECODER - A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines. | 09-27-2012 |
20120250444 | PSEUDO-INVERTER CIRCUIT ON SeOI - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 10-04-2012 |
20130015442 | BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME - Methods of forming semiconductor structures include transferring a portion ( | 01-17-2013 |
20130029474 | METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER ONTO A SUPPORT SUBSTRATE - A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization. | 01-31-2013 |
20130100749 | NANO-SENSE AMPLIFIER - A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. | 04-25-2013 |
20140015023 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-16-2014 |