Patent application number | Description | Published |
20080301474 | Performance Analysis Based System Level Power Management - A multiprocessor system-on-chip | 12-04-2008 |
20090217095 | MEANS AND METHOD FOR DEBUGGING - A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register. | 08-27-2009 |
20090265582 | DATA PROCESSING SYSTEM AND METHOD OF DEBUGGING - A data processing system is provided. The data processing system comprises at least one processor (P) for processing data according to a set of instructions. The processors are coupled by a bus means (BM). Furthermore, a debugging means (DM) is provided to detect the occurrence of events and the corresponding point of time of the occurrence on the bus means (BM). If predefined events occur at, within and/or after/before predefined points in time, the debugging mode is switched on. | 10-22-2009 |
20090300631 | DATA PROCESSING SYSTEM AND METHOD FOR CACHE REPLACEMENT - A data processing system is provided with at least one processing unit ( | 12-03-2009 |
20100223438 | REGION PROTECTION UNIT, INSTRUCTION SET AND METHOD FOR PROTECTING A MEMORY REGION - A memory region protection unit is disclosed that comprises a first register for storing a memory region address, a second register for storing the memory region size, an arithmetic function block for executing an arithmetic function on a memory address provided to the region protection unit and the address value in the first register. The unit further has a comparator for comparing the output of the arithmetic function block with the size value in the second register, the comparator being coupled to an output for signalling the validity of the memory address on the bus The region protection unit has a controller configured to retrieve the memory region address and the memory region size from instructions issued to the region protection unit for associating the unit with said region, and to dissociate the unit from its memory region in response to a further instruction. | 09-02-2010 |
20140136226 | SYSTEM FOR MANAGING CARDIOVASCULAR HEALTH STATUS | 05-15-2014 |
20140379365 | MEANINGFUL PRESENTATION OF HEALTH RESULTS TO DETERMINE NECESSARY LIFESTYLE CHANGES - A medical system ( | 12-25-2014 |
Patent application number | Description | Published |
20090070532 | System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation - A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case. | 03-12-2009 |
20090070631 | System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation - A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor. | 03-12-2009 |
20100011248 | LIGHT WEIGHT AND HIGH THROUGHPUT TEST CASE GENERATION METHODOLOGY FOR TESTING CACHE/TLB INTERVENTION AND DIAGNOSTICS - A test case manager selects a first test case and a second test case from a plurality of test cases. The test case manager provides the first test case to a first processor and provides the second test case to a second processor. As such, the first processor executes the first test case and the second processor executes the second test case. After the execution, the test case manager loads the first test case onto the second processor and loads the second test case onto the first processor. In turn, the first processor executes the second test case and the second processor executes the first test case. | 01-14-2010 |