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| 20090047583 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 02-19-2009 |
| 20090104540 | Graded lithographic mask - In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein the metallic layer has tapered edges with a graded transparency. The lithographic mask, along with etching processes may be used to transfer a pattern | 04-23-2009 |
| 20110045388 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 02-24-2011 |
| 20110256644 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 10-20-2011 |
| 20130130163 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 05-23-2013 |
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| 20080265340 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 10-30-2008 |
| 20100032774 | LOW COST HIGH VOLTAGE POWER FET AND FABRICATION - A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life. | 02-11-2010 |
| 20110084324 | RADIATION HARDENED MOS DEVICES AND METHODS OF FABRICATION - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 04-14-2011 |
| 20110256687 | Method for Fabricating Through Substrate Microchannels - A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device. | 10-20-2011 |
| 20120038005 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 02-16-2012 |
| 20130320808 | INTEGRATED RESONATOR WITH A MASS BIAS - An integrated resonator apparatus includes a piezoelectric resonator and an acoustic Bragg reflector formed adjacent the piezoelectric resonator. The integrated resonator apparatus also includes a mass bias formed over the Bragg reflector on a side of the piezoelectric resonator opposite the piezoelectric resonator. | 12-05-2013 |
| 20130321101 | TEMPERATURE-CONTROLLED INTEGRATED PIEZOELECTRIC RESONATOR APPARATUS - An integrated resonator apparatus comprises a piezoelectric resonator, an acoustic Bragg reflector coupled to the piezoelectric resonator, and a substrate on which the acoustic Bragg reflector is disposed. The apparatus also includes an active heater layer covering the piezoelectric resonator. Heat produced by the active heater layer is controllable by an amount of current provided through the heater layer. | 12-05-2013 |
| 20150129986 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 05-14-2015 |
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| 20140136793 | SYSTEM AND METHOD FOR REDUCED CACHE MODE - A system and method are described for dynamically changing the size of a computer memory such as level 2 cache as used in a graphics processing unit. In an embodiment, a relatively large cache memory can be implemented in a computing system so as to meet the needs of memory intensive applications. But where cache utilization is reduced, the capacity of the cache can be reduced. In this way, power consumption is reduced by powering down a portion of the cache. | 05-15-2014 |
| 20150100764 | DYNAMICALLY DETECTING UNIFORMITY AND ELIMINATING REDUNDANT COMPUTATIONS TO REDUCE POWER CONSUMPTION - One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output. Advantageously, by exploiting the uniformity of data to reduce the number of execution units that execute, the SM dramatically reduces the power consumption compared to conventional SMs. | 04-09-2015 |
| 20150113254 | EFFICIENCY THROUGH A DISTRIBUTED INSTRUCTION SET ARCHITECTURE - A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction. | 04-23-2015 |
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| 20090192298 | Through-bond energy transfer cassettes, systems and methods - The present disclosure relates, according to some embodiments, to compositions, systems, and methods for preparing and using fluorescent through-bond energy transfer cassettes. | 07-30-2009 |
| 20090264315 | DIPEPTIDE MIMICS, LIBRARIES COMBINING TWO DIPEPTIDE MIMICS WITH A THIRD GROUP, AND METHODS FOR PRODUCTION THEREOF - Monovalent compounds having moieties comprising at least one amino acid side chain are bound to a core molecule, which also comprises a nucleophilic moiety bound to said core molecule. Monovalent compounds also comprise a macrocyclic ring, a nucleophilic moiety, and a spacer group. Monovalent compounds may be combined into bivalent and trivalent compounds, some of which may have a labeling tag. Methods of production of bivalent compounds and contemplated uses thereof are disclosed. | 10-22-2009 |
| 20110212955 | ROSAMINE DERIVATIVES AS AGENTS FOR THE TREATMENT OF CANCER - The present invention relates to a new class of rosamine derivatives, in one embodiment, the compounds have the structure (I) or any pharmaceutically acceptable salt or solvate thereof, wherein: R | 09-01-2011 |
| 20120232268 | Dipeptide Mimics, Libraries Combining Two Dipeptide Mimics with a Third Group, and Methods for Production Thereof - Monovalent compounds having moieties comprising at least one amino acid side chain are bound to a core molecule, which also comprises a nucleophilic moiety bound to said core molecule. Monovalent compounds also comprise a macrocyclic ring, a nucleophilic moiety, and a spacer group. Monovalent compounds may be combined into bivalent and trivalent compounds, some of which may have a labeling tag. Methods of production of bivalent compounds and contemplated uses thereof are disclosed. | 09-13-2012 |
| 20130288331 | PEPTIDOMIMETIC COMPOUNDS AND RELATED METHODS - Provided herein are compounds and methods of using same for the perturbation and/or inhibition of protein-protein interactions. Also provided herein is a data mining method useful for the identification of protein-protein interactions that may be inhibited by these compounds. | 10-31-2013 |
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| 20130151576 | APPARATUS AND METHOD FOR ROUNDING A FLOATING-POINT VALUE TO AN INTEGRAL FLOATING-POINT VALUE - Processing circuitry is provided to perform an operation FRINT for rounding a floating-point value to an integral floating-point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value, adding circuitry for adding the rounding value to the significand of the floating-point value to generate a sum value, mask generating circuitry for generating a mask for clearing fractional-valued bits of the sum value, and masking circuitry for applying the mask to the sum value to generate the integral floating-point value. | 06-13-2013 |
| 20130304785 | APPARATUS AND METHOD FOR PERFORMING A CONVERT-TO-INTEGER OPERATION - A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The convert-to-integer operation uses round-to-nearest, ties away from zero, rounding (RNA rounding). The operation is performed by generating an intermediate value based on the floating-point value, adding a rounding value to the intermediate value to generate a sum value, and outputting the integer-valued bits of the sum value as the rounded two's complement integer value. If the floating-point value is negative, then the intermediate value is generated by inverting the bits without adding a bit value of 1 to a least significant bit of the inverted value. | 11-14-2013 |
| 20130339412 | DATA PROCESSING APPARATUS AND METHOD - Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle. | 12-19-2013 |
| 20140040334 | DATA PROCESSING APPARATUS AND METHOD FOR REDUCING THE SIZE OF A LOOKUP TABLE - A data processing apparatus is provided with lookup table circuitry for receiving from the processing circuitry an n-bit input data value, and for returning to the processing circuitry an output data value. The lookup table circuitry provides a plurality of entries identifying possible input data values and corresponding output data values, with the plurality of entries being less than 2 | 02-06-2014 |
| 20150039665 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION - A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N| 02-05-2015 | |
| 20150199173 | MULTIPLY ADDER - A floating point multiply add circuit | 07-16-2015 |
| 20150227346 | COMPARING A RUNLENGTH OF BITS WITH A VARIABLE NUMBER - Processing circuitry | 08-13-2015 |
| 20150254066 | DATA PROCESSING APPARATUS AND METHOD FOR MULTIPLYING FLOATING POINT OPERANDS - A data processing apparatus and method are provided for multiplying first and second normalised floating point operands in order to generate a result, each normalised floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalised version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalised floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalised result significand. Thereafter, the normalised result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, whilst correctly rounding the result in situations where the result is subnormal. | 09-10-2015 |
| 20150261498 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A SHIFT FUNCTION ON A BINARY NUMBER - A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number. Once the count value is available from the count determination circuitry, fine shifting circuitry then performs a further shift operation on the intermediate binary number, based on the count value output by the count determination circuitry, in order to produce the result binary number. This provides an efficient mechanism for performing a shift function on a binary number, whilst still capturing the count value from the count determination circuitry. | 09-17-2015 |
| 20150269981 | PREDICTING SATURATION IN A SHIFT OPERATION - Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results. | 09-24-2015 |
| 20150378681 | APPARATUS AND METHOD FOR EFFICIENT DIVISION PERFORMANCE - A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2 | 12-31-2015 |
