Patent application number | Description | Published |
20080265428 | VIA AND SOLDER BALL SHAPES TO MAXIMIZE CHIP OR SILICON CARRIER STRENGTH RELATIVE TO THERMAL OR BENDING LOAD ZERO POINT - A method of modifying via and solder ball shapes for maximizing semiconductor chip or silicon carrier strengths relative to thermal expansion and bending load zero points. The method entails modifying circular annular vias into elliptical annular vias so as to reduce stress concentration factors in the chip or carrier at the vias and solder balls. The reduction in the stress concentration is effected in the semiconductor chip or silicon carrier in regions proximate the vias and in wiring layers at the ends of the vias. | 10-30-2008 |
20080298016 | COOLING AN ELECTRONIC DEVICE UTILIZING SPRING ELEMENTS WITH FINS - A method for cooling an electronic device includes forming a spring structure by coupling a plurality of spring elements with a fin portion oriented at an angle, wherein a first end of the fin portion has a narrowed tip; coupling the spring structure with a planar heat-conducting material to form a first heat-conducting layer; positioning the first heat-conducting layer such that the planar heat-conducting material is on top; and placing the first heat-conducting layer over the electronic device such that the fin portion is oriented at an angle toward the electronic device, and such that the narrowed tip of the fin portion is in contact with the top surface of the electronic device. | 12-04-2008 |
20090027860 | COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE - An integrated circuit package includes: a substrate; an electronic circuit located on the substrate, the electronic circuit comprising a topography of at least one level; a cooling device located over the electronic circuit; a compliant interface disposed between the electronic circuit and the cooling device, wherein the compliant interface comprises a first surface and a second surface and wherein the first surface is in thermal contact with the electronic circuit, and wherein the compliant interface is preformed from a compliant material such that the first surface substantially conforms to the topography of the electronic circuit. | 01-29-2009 |
20110108958 | Metal Oxide Semiconductor (MOS)-Compatible High-Aspect Ratio Through-Wafer Vias and Low-Stress Configuration Thereof - A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed. | 05-12-2011 |
20110171756 | REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD - An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts. | 07-14-2011 |
20130039733 | PICK AND PLACE TAPE RELEASE FOR THIN SEMICONDUCTOR DIES - Pick and place tape release techniques and tools that allow thin, fragile semiconductor dies to be removed from wafer tape with reduced tape release forces applied to the semiconductor dies. For example, a method for removing semiconductor die from wafer tape includes mounting a wafer ring having wafer tape and one or more dies attached to the wafer tape, and aligning an ejector pin assembly under a target die to be removed from the wafer tape. The ejector pin assembly includes a vacuum housing, an ejector pin, a suction plate, and an aperture formed in the suction plate in alignment with the ejector pin. A vacuum is generated in the vacuum housing to draw the tape against a surface of the suction plate. The ejector pin is extended through the vacuum housing out from the aperture of the suction plate to push against a backside of the target die and release the tape from the backside of the target die, and as the tape is released from the backside of the target die, the tape is drawn down against the suction plate by suction force of the vacuum. | 02-14-2013 |
20130093032 | SEMICONDUCTOR TRENCH INDUCTORS AND TRANSFORMERS - Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density. | 04-18-2013 |
20130106552 | INDUCTOR WITH MULTIPLE POLYMERIC LAYERS | 05-02-2013 |
20130120872 | MAGNETIC WRITER HAVING MULTIPLE GAPS WITH MORE UNIFORM MAGNETIC FIELDS ACROSS THE GAPS - A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux. | 05-16-2013 |
20130176095 | INDUCTOR WITH LAMINATED YOKE - A thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses. | 07-11-2013 |
20130314192 | INDUCTOR WITH STACKED CONDUCTORS - A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material. | 11-28-2013 |
20140013606 | UNDERFILL MATERIAL DISPENSING FOR STACKED SEMICONDUCTOR CHIPS - A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion. | 01-16-2014 |
20140026431 | UNDERFILL MATERIAL DISPENSING FOR STACKED SEMICONDUCTOR CHIPS - A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion. | 01-30-2014 |
20140061853 | PLATED LAMINATION STRUCTURES FOR INTEGRATED MAGNETIC DEVICES - Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure. | 03-06-2014 |
20140126078 | MAGNETIC WRITER HAVING MULTIPLE GAPS WITH MORE UNIFORM MAGNETIC FIELDS ACROSS THE GAPS - A magnetic device according to one embodiment includes a source of flux; a magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and riot positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux. | 05-08-2014 |
20140190003 | INDUCTOR WITH LAMINATED YOKE - A method for forming a thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses. | 07-10-2014 |
20150061815 | PLANAR INDUCTORS WITH CLOSED MAGNETIC LOOPS - A planar closed-magnetic-loop inductor and a method of fabricating the inductor are described. The inductor includes a first material comprising a cross-sectional shape including at least four segments, at least one of the at least four segments including a first edge and a second edge on opposite sides of an axial line through the at least one of the at least four segments. The first edge and the second edge are not parallel. | 03-05-2015 |
20150064362 | PLANAR INDUCTORS WITH CLOSED MAGNETIC LOOPS - A planar closed-magnetic-loop inductor and a method of fabricating the inductor are described. The inductor includes a first material comprising a cross-sectional shape including at least four segments, at least one of the at least four segments including a first edge and a second edge on opposite sides of an axial line through the at least one of the at least four segments. The first edge and the second edge are not parallel. | 03-05-2015 |