Patent application number | Description | Published |
20090013211 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 01-08-2009 |
20090319877 | SYSTEMS, METHODS, AND APPARATUSES TO TRANSFER DATA AND DATA MASK BITS IN A COMMON FRAME WITH A SHARED ERROR BIT CODE - Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame. | 12-24-2009 |
20100281315 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 11-04-2010 |
20110066919 | MEMORY ERROR DETECTION AND/OR CORRECTION - An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error. | 03-17-2011 |
20110131370 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 06-02-2011 |
20110138261 | METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE - A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command. | 06-09-2011 |
20110145506 | Replacing Cache Lines In A Cache Memory - In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed. | 06-16-2011 |
20110154152 | ERROR CORRECTION MECHANISMS FOR 8-BIT MEMORY DEVICES - Described herein are 8-bit wide data error detection and correction mechanisms that require fewer memory chips and therefore provide reduces system complexity and reduced system power consumption as compared to traditional mechanisms. This technique relies on testing a fixed set of possible solutions in order to correct the fault. This error code provides a very high error detection rate, but requires a set of error trials to correct the detected faults. The extra correction latency for infrequent errors may be acceptable given a low frequency. For repeated corrections, a log may be maintained to simplify error correction. | 06-23-2011 |
20120102256 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 04-26-2012 |
20120331356 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 12-27-2012 |
20130097371 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 04-18-2013 |
20130117641 | METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE - A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command. | 05-09-2013 |
Patent application number | Description | Published |
20110153515 | Distributed capture system for use with a legacy enterprise content management system - A distributed capture system is disclosed which enables digital content to be captured in various formats and interfaced with a plurality ECM) platforms which enables the distributed capture system to be seamlessly integrated with a customer's legacy ECM system. The system is configured to receive various financial records that are normally created at a financial institution, such as loan applications and customer signature cards, in various formats, such as Microsoft Word, PDF, and Printer Control Language (PCL). The financial records are directed to a virtual printer and converted to a TIFF format. The print stream associated with the text embedded in the TIFF image of the financial record is captured and compared with document classification template. The document classification template allows the document to be automatically classified and indexed. Documents are then sent to the ECM interface. The ECM interface allows financial records that are normally created at the financial institution to be converted to electronic form and stored in the financial institution's legacy ECM. By eliminating the need to purchase a new ECM, the need to convert existing data to the format of the legacy ECM is obviated. | 06-23-2011 |
20150186365 | DISTRIBUTED CAPTURE SYSTEM FOR USE WITH A LEGACY ENTERPRISE CONTENT MANAGEMENT SYSTEM - A distributed capture system is disclosed which enables digital content to be captured in various formats and interfaced with a plurality ECM) platforms which enables the distributed capture system to be seamlessly integrated with a customer's legacy ECM system. The system is configured to receive various financial records that are normally created at a financial institution, such as loan applications and customer signature cards, in various formats, such as Microsoft Word, PDF, and Printer Control Language (PCL). The financial records are directed to a virtual printer and converted to a TIFF format. The print stream associated with the text embedded in the TIFF image of the financial record is captured and compared with document classification template. The document classification template allows the document to be automatically classified and indexed. Documents are then sent to the ECM interface. The ECM interface allows financial records that are normally created at the financial institution to be converted to electronic form and stored in the financial institution's legacy ECM. By eliminating the need to purchase a new ECM, the need to convert existing data to the format of the legacy ECM is obviated. | 07-02-2015 |
Patent application number | Description | Published |
20150270046 | MAGNETIC CONNECTION AND ALIGNMENT OF CONNECTIBLE DEVICES - A first and second electronic device each including a connection surface and a magnetic element. The first and second devices may be in contact along the respective connection surfaces. The magnetic elements may be configured to align the first and second devices by moving either or both of the first and second devices relative to each other to achieve an aligned position. The magnetic element may also be operative to resist disconnection of first and second electronic devices when in the aligned position. | 09-24-2015 |
20150270058 | MAGNETIC SHIELDING IN INDUCTIVE POWER TRANSFER - A first electronic device connects with an second electronic device. The first electronic device may include a first connection surface and an inductive power transfer receiving coil and a first magnetic element positioned adjacent to the first connection surface. The second electronic device may similarly include a second connection surface and an inductive power transfer transmitting coil and second magnetic element positioned adjacent to the second connection surface. In the aligned position, alignment between the electronic devices may be maintained by magnetic elements and the inductive power coils may be configured to exchange power. The magnetic elements and/or the inductive power coils may include a shield that is configured to minimize or reduce eddy currents caused in the magnetic elements by the inductive power coils. | 09-24-2015 |
20150280483 | TEMPERATURE MANAGEMENT FOR INDUCTIVE CHARGING SYSTEMS - A thermal management system for an electromagnetic induction-power transfer system. The system may include a charging apparatus including a housing that defines an interface surface. An accessory or induction-power consuming apparatus may be positioned proximate to the interface surface. The housing of the charging apparatus may include a power source and a power-transferring coil coupled to the power source and positioned below the interface surface. A thermal mass may be positioned within the housing and spaced apart from the interface surface. The housing may include a thermal path that is configured to conduct heat from the interface surface to the thermal mass. | 10-01-2015 |
20150308470 | MAGNETIC PRELOADING OF JOINTS - A first component is coupled to a second component by one or more joints. Magnetic force between at least a first magnetic and second magnetic unit preloads the joint by placing the joint in compression. The first and second magnetic units may be respectively coupled to the first and second components. The magnetic force acts as a retentive force between coupled components and/or the joint and operates to resist one or more tensile and/or other opposing forces. In some cases, the first magnetic unit may be a shield, such as a direct current shield, that protects one or more components from a magnetic field of the second magnetic unit. | 10-29-2015 |
20150348697 | COIL CONSTRUCTIONS FOR IMPROVED INDUCTIVE ENERGY TRANSFER - An inductor coil for an inductive energy transfer system includes multiple layers of a single wire having windings that are interlaced within at least two of the multiple layers such that both an input end and an output end of the wire enter and exit the coil on a same side of the coil. The input end and the output end of the wire may abut one another at the location where the input and output wires enter and exit the inductor coil. The wire can include one or more bundles of strands and the strands in each bundle are twisted around an axis extending along a length of the wire, and when there are at least two bundles, the bundles may be twisted around the axis. At least one edge of the inductor coil can be formed into a variety of shapes, such as in a curved shape. | 12-03-2015 |
20150349539 | Reducing the Impact of an Inductive Energy Transfer System on a Touch Sensing Device - A transmitter device for an inductive energy transfer system can include a DC-to-AC converter operably connected to a transmitter coil, a first capacitor connected between the transmitter coil and one output terminal of the DC-to-AC converter, and a second capacitor connected between the transmitter coil and another output terminal of the DC-to-AC converter. One or more capacitive shields can be positioned between the transmitter coil and an interface surface of the transmitter device. A receiver device can include a touch sensing device, an AC-to-DC converter operably connected to a receiver coil, a first capacitor connected between the receiver coil and one output terminal of the AC-to-DC converter, and a second capacitor connected between the receiver coil and another output terminal of the AC-to-DC converter. One or more capacitive shields can be positioned between the receiver coil and an interface surface of the receiver device. | 12-03-2015 |
20150371768 | METHODS FOR FORMING SHIELD MATERIALS ONTO INDUCTIVE COILS - Methods of and systems for directing flux from a transmit coil to a receive coil within an inductive power transfer system are disclosed. For example, a transmit coil may be shielded with a contoured shield made from a ferromagnetic material. The contoured shield may contour to several surfaces of the transmit coil so as to define a single plane through which flux may be directed to a receive coil. | 12-24-2015 |
20160064137 | CAPACITIVELY BALANCED INDUCTIVE CHARGING COIL - An inductor coil includes a wire which is wound in alternating layers such that the surface area of the wire in each winding viewed from above or below the coil is substantially equal in each half of the coil defined by a line bisecting the center point in each layer. The layers are also wound in a serpentine fashion to balance the capacitance between layers. The substantially equal surface area of wire in each half of a coil layer and in adjacent coil layers results in a balanced capacitance of the coil which, in turn, results in reduced common mode noise. | 03-03-2016 |
20160064141 | MAGNETICALLY DOPED ADHESIVE FOR ENHANCING MAGNETIC COUPLING - In some embodiments, an electronic device includes an electronic component that is at least partially encapsulated by an adhesive doped with soft magnetic material that functions as an EMI shield for the electronic component. In various embodiments, an electronic device includes a first magnetic component separated from a second magnetic component by a gap within which is positioned an adhesive doped with soft magnetic material. The doped adhesive is positioned in a magnetic path between the first and second magnetic components and aids in magnetically coupling the first and second magnetic components and/or guides magnetic flux between the first and second magnetic components. | 03-03-2016 |