| Patent application number | Description | Published |
|---|
| 20090184742 | Externally Synchronizing Multiphase Pulse Width Modulation Signals - Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to “capture” the value of the master time base counter at the occurrence of the rising edge of the external sync signal. This captured counter value is then provided to the local time bases of each of the phase PMW signal generators as the effective PWM period instead of locally stored PWM period values of each PWM signal generator. The captured time base value provided to the individual PWM generator time bases insures that the individual PWM generators remain properly synchronized to the master time base throughout the PWM cycles of all of the phases. | 07-23-2009 |
| 20110222322 | DIGITAL DEVICE WITH BOOT STRAP CIRCUIT STIMULATOR - A digital device generates a fixed duty cycle signal with an internal oscillator after a Power-On-Reset (POR). This fixed duty cycle signal is output on a signal pin that normally is used for a PWM control signal. The fixed duty cycle signal is used to stimulate the voltage generation circuits so as to power up the digital device for initialization thereof. Once the digital device has powered-up and initialized, the digital device switches over to normal operation for control of the power system. | 09-15-2011 |
| 20130076417 | MAINTAINING PULSE WIDTH MODULATION DATA-SET COHERENCY - Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle. | 03-28-2013 |
| 20130082747 | VARIABLE FREQUENCY RATIOMETRIC MULTIPHASE PULSE WIDTH MODULATION GENERATION - Groups of phase shifted PWM signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals. | 04-04-2013 |
| 20130082794 | EXTENDING PULSE WIDTH MODULATION PHASE OFFSET - Extending pulse width modulation phase offset when generating phase shifted groups of pulse width modulation (PWM) signals is accomplished with a separate phase counter that is independent of the time-base counters used in traditional PWM generation circuits and that is prevented from being retriggered until an existing duty cycle has completed. This is accomplished with a phase offset counter, a phase comparator and a circuit that is triggered via a master time base for overall synchronization of the multi-phase PWM signal generation. | 04-04-2013 |
| 20130082795 | REPETITIVE SINGLE CYCLE PULSE WIDTH MODULATION GENERATION - Multiple pulse width modulation (PWM) generators each have a separate phase offset counter creating a phase shift. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. A master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. Then, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals. | 04-04-2013 |
| 20130141058 | INTEGRATED CIRCUIT DEVICE WITH INTEGRATED VOLTAGE CONTROLLER - An integrated circuit device has a housing having a plurality of external pins; a central processing unit (CPU) operating at an internal core voltage and being coupled with the plurality of pins; and an internal switched mode voltage regulator receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins of the plurality of external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins. | 06-06-2013 |
| 20130145066 | ANALOG-TO-DIGITAL CONVERTER WITH EARLY INTERRUPT CAPABILITY - An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened. | 06-06-2013 |
| 20130147446 | INTEGRATED CIRCUIT DEVICE WITH TWO VOLTAGE REGULATORS - An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins. | 06-13-2013 |
| 20140075052 | PERIPHERAL TRIGGER GENERATOR - A microcontroller includes a central processing unit (CPU); a plurality of peripheral units; and a peripheral trigger generator comprising a user programmable state machine, wherein the peripheral trigger generator is configured to receive a plurality of input signals and is programmable to automate timing functions depending on at least one of said input signals and generate at least one output signal. | 03-13-2014 |
| 20140139278 | Variable Frequency Ratiometric Multiphase Pulse Width Modulation Generation - Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals. | 05-22-2014 |
| 20140240020 | CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING - A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators. | 08-28-2014 |
| 20140266833 | Pulse Density Digital-to-Analog Converter with Slope Compensation Function - A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter. | 09-18-2014 |
| 20150019847 | Programmable CPU Register Hardware Context Swap Mechanism - A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context. | 01-15-2015 |
