Patent application number | Description | Published |
20090108435 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 04-30-2009 |
20090308578 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 12-17-2009 |
20090311826 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 12-17-2009 |
20100053890 | COOLING SYSTEM FOR AN ELECTRONIC COMPONENT SYSTEM CABINET - An electronic component system cabinet includes a plurality of electronic component system bays, and a plurality of electronic component systems mounted in respective ones of the plurality of electronic component system bays. The electronic component system cabinet further includes a cooling system including a plurality of coolant reservoirs. Each of the plurality of coolant reservoirs is associated with at least one of the plurality of electronic component system bays. The cooling system further includes at least one pump fluidly connected to each of the plurality of coolant reservoirs. The at least one pump is selectively operated to circulate a supply of coolant to each of the plurality of coolant reservoirs. | 03-04-2010 |
20100308316 | Electronic Device Having an Electrode With Enhanced Injection Properties - An electronic device having an electrode with enhanced injection properties comprising a first electrode and a first layer of cross-linked molecular charge transfer material on the first electrode. The cross-linked molecular charge transfer material may be an acceptor, which may consist of at least one of: TNF, TN9(CN)2F, TeNF, TeCIBQ, TCNB, DCNQ, and TCAQ. The cross-linked molecular charge transfer material may also be a donor, which may consist of at least one of: Terpy, Ru(terpy)2 TTN, and crystal violet. | 12-09-2010 |
20120105144 | Optimized Semiconductor Packaging in a Three-Dimensional Stack - A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120105145 | Thermal Power Plane for Integrated Circuits - A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120106074 | Heat Sink Integrated Power Delivery and Distribution for Integrated Circuits - A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120186793 | INTEGRATED DEVICE WITH DEFINED HEAT FLOW - An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap. | 07-26-2012 |
20120273183 | COOLANT PUMPING SYSTEM FOR MOBILE ELECTRONIC SYSTEMS - A coolant pumping system for a mobile electronic system includes a coolant reservoir containing a coolant, a heat exchanger member fluidly connected to the coolant reservoir, and a mass moveably mounted to the mobile electronic system. The mass is moved along at least one axis in response to at least one of accelerations and orientation changes of the mobile electronic system. The coolant system further includes a force transfer member operatively connected between the mass and the coolant reservoir. The force transfer member urges the coolant from the coolant reservoir through the heat exchanger member in response to movements of the mass. A gear member is operatively connected between the mass and the force transfer member. | 11-01-2012 |
20120290999 | Optimized Semiconductor Packaging in a Three-Dimensional Stack - A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 11-15-2012 |
20120325144 | Electronic Device Having an Electrode with Enhanced Injection Properties - An electronic device having an electrode with enhanced injection properties comprising a first electrode and a first layer of cross-linked molecular charge transfer material on the first electrode. The cross-linked molecular charge transfer material may be an acceptor, which may consist of at least one of: TNF, TN9(CN)2F, TeNF, TCNB, DCNQ, and TCAQ. The cross-linked molecular charge transfer material may also be a donor, which may consist of at least one of: Terpy, Ru(terpy)2 TTN, and crystal violet. | 12-27-2012 |
20130331996 | Optimizing Heat Transfer in 3-D Chip-Stacks - A computer-implemented method, system, and article of manufacture for optimizing heat transfer in a 3-D chip-stack. The method includes the steps of: receiving a heat-removal effectiveness parameter for a plurality of channel-region areas in the chip-stack, receiving at least one of a flow value and temperature value for at least two of the channel-region areas, comparing the received values for different channel-region areas, and adjusting a flow rate of a liquid flowing to at least one of the two channel-region areas based on the heat-removal effectiveness parameter of the channel-region area receiving the adjustment and the results of the comparison step, where at least one step is carried out using a computer device. | 12-12-2013 |
20140084443 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 03-27-2014 |
20140084448 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output. | 03-27-2014 |
20140095121 | TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY - A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink. | 04-03-2014 |