Patent application number | Description | Published |
20110108920 | HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE - A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure. | 05-12-2011 |
20110108961 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device. | 05-12-2011 |
20110111592 | ANGLE ION IMPLANT TO RE-SHAPE SIDEWALL IMAGE TRANSFER PATTERNS - A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features. | 05-12-2011 |
20110115022 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers. | 05-19-2011 |
20110127582 | MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed. | 06-02-2011 |
20110127588 | ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES - A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures. | 06-02-2011 |
20110129978 | METHOD AND STRUCTURE FOR FORMING FINFETS WITH MULTIPLE DOPING REGIONS ON A SAME CHIP - A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins. | 06-02-2011 |
20110227165 | HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE - A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure. | 09-22-2011 |
20110291100 | DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material. | 12-01-2011 |
20110291189 | THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed. | 12-01-2011 |
20110291202 | DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions. | 12-01-2011 |
20110309445 | SEMICONDUCTOR FABRICATION - Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics. | 12-22-2011 |
20120074494 | STRAINED THIN BODY SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DEVICE - A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress. | 03-29-2012 |
20120193710 | DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions. | 08-02-2012 |
20120280283 | MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed. | 11-08-2012 |
20120280365 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography. | 11-08-2012 |
20130001702 | ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES - A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas formed in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures. | 01-03-2013 |
20130012025 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device. | 01-10-2013 |
20130015525 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOSAANM Cheng; KangguoAACI AlbanyAAST NYAACO USAAGP Cheng; Kangguo Albany NY USAANM Doris; Bruce B.AACI AlbanyAAST NYAACO USAAGP Doris; Bruce B. Albany NY USAANM Khakifirooz; AliAACI San JoseAAST CAAACO USAAGP Khakifirooz; Ali San Jose CA USAANM Haran; Balasubramanian S.AACI AlbanyAAST NYAACO USAAGP Haran; Balasubramanian S. Albany NY US - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 01-17-2013 |
20130056802 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of | 03-07-2013 |
20130069196 | STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS - The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented. | 03-21-2013 |
20130146975 | SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI - A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device. | 06-13-2013 |
20130249002 | Structure and method to improve etsoi mosfets with back gate - A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole. | 09-26-2013 |
20140124860 | METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET - Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. | 05-08-2014 |