Patent application number | Description | Published |
20080205114 | Semiconductor memory device and method of operating same - There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row. | 08-28-2008 |
20090231898 | Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line. | 09-17-2009 |
20110249499 | Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line. | 10-13-2011 |
Patent application number | Description | Published |
20130302198 | SCROLL REFRIGERATION COMPRESSOR - The scroll refrigeration compressor includes a stationary volute and a moving volute provided with spiral wraps defining variable-volume compression chambers, a separating member sealably mounted on a plate of the stationary volute so as to allow a relative movement between the separating member and the stationary volute, a delivery chamber at least partially defined by the separating member and the sealed casing. The compressor further includes a bypass passage arranged to communicate the delivery chamber with an intermediate compression chamber, and a anti-return device comprising a closing member movable between closing and opening positions for closing and opening the bypass passage, and an enclosure, positioned between the separating member and the plate of the stationary volute, including a first portion sealably mounted in a housing defined by the separating member and oriented substantially parallel to the longitudinal axis of the compressor. | 11-14-2013 |
20130315768 | SCROLL REFRIGERATION COMPRESSOR - The scroll compressor includes stationary and moving volutes each including a scroll plate provided with a spiral wrap, the spiral wraps defining the variable-volume compression chambers, a delivery conduit including a first end emerging in a central compression chamber and a second end designed to be communicated with a delivery chamber, a delivery valve movable between closing and opening positions for closing and opening at least one delivery opening arranged to communicate the delivery conduit and the delivery chamber, at least one bypass valve associated with a bypass passage arranged to communicate the delivery chamber with an intermediate compression chamber. The compressor includes a retaining plate mounted on the scroll plate of the stationary scroll and on which first and second retaining elements are formed, the latter being arranged to limit respectively the amplitude of movement of the delivery valve and of each bypass valve toward the opening position thereof. | 11-28-2013 |