Patent application number | Description | Published |
20090153211 | Integrated circuit device core power down independent of peripheral device operation - In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited. | 06-18-2009 |
20090201082 | INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION - A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands. | 08-13-2009 |
20090204834 | SYSTEM AND METHOD FOR USING INPUTS AS WAKE SIGNALS - A system and method for waking up a portion of a programmable system on a chip (SoC). The system includes a power management unit for controlling power levels to the SoC and one or more inputs for receiving inputs from a coupled device. The system further includes a power management interface coupled to the one or more inputs. The power management interface signals the power management unit to adjust power levels to the SoC in response to receiving a signal via the one or more inputs corresponding to a wake event. | 08-13-2009 |
20090204835 | USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS - In a programmable SoC (system-on-a-chip) integrated circuit device, a method for optimizing power efficiency for a requested device functionality. The method includes determining a requested device functionality, and in response to the requested device functionality, turning on power for a selected one or more power domains out of a plurality of power domains included within the integrated circuit device. Each of the power domains has its own respective voltage rail to obtain power. The method further includes turning on one or more power islands out of a plurality of power islands included within the integrated circuit device. The requested device functionality is then implemented using one or more functional blocks wherein each functional block is configured to provide a specific device functionality. | 08-13-2009 |
20090256607 | POWERED RING TO MAINTAIN IO INDEPENDENT OF THE CORE OF AN INTEGRATED CIRCUIT DEVICE - In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode. | 10-15-2009 |
20090259425 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CALIBRATION - A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage. | 10-15-2009 |
20090309243 | MULTI-CORE INTEGRATED CIRCUITS HAVING ASYMMETRIC PERFORMANCE BETWEEN CORES - An integrated circuit in one embodiment includes asymmetric cores and an asymmetric core control circuit. At least one of the asymmetric cores is a different implementation of substantially the same function or subset of functionality as another core. The asymmetric core control circuit determines a performance parameter of an integrated circuit. The performance parameter may be the workload, the operating frequency, power consumption, quality of service, operating temperature or the like of the integrated circuit or a given portion of the integrated circuit. If the performance parameter is within a first range, the asymmetric core control circuit utilizes a first core to perform a function of the integrated circuit and idles a second core that is a different implementation of substantially the same function. If the performance parameter is within a second range, the core control circuit utilizes the second core to perform the function and idles the first core. | 12-17-2009 |
20110213947 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
20110213950 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
20110213998 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
20120331275 | SYSTEM AND METHOD FOR POWER OPTIMIZATION - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 12-27-2012 |
20120331319 | SYSTEM AND METHOD FOR POWER OPTIMIZATION - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 12-27-2012 |
20140047257 | POWER MANAGEMENT TECHNIQUES FOR USB INTERFACES - Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state. | 02-13-2014 |
20140176116 | QUANTIFYING SILICON DEGRADATION IN AN INTEGRATED CIRCUIT - A first instance and a second instance of an oscillating circuit are each formed as part of an integrated circuit and are used to monitor degradation over time of one or more portions of the integrated circuit. The first instance of the oscillating circuit is configured to be coupled to a power source during normal operation of the integrated circuit and the second instance is configured to be decoupled from the power source. Over the lifetime of the integrated circuit, the first instance undergoes degradation from use while the second instance of the oscillating circuit remains unpowered, therefore experiencing essentially no use-related degradation. During a testing operation, the second instance can be used as a reference circuit that accurately quantifies use-related degradation of the first instance of the oscillating circuit and, by extension, one or more portions of the integrated circuit. | 06-26-2014 |
20150061633 | TECHNIQUE FOR SUPPLYING POWER TO A LOAD VIA VOLTAGE CONTROL AND CURRENT CONTROL MODES OF OPERATION - A regulator draws power from a battery or power delivery system and supplies regulated power to a load according to alternating modes of operation. In a voltage control mode, the regulator supplies power with a nominal voltage level and a fluctuating current level that is allowed to float according to the current demands of the load. When the load demands an amount of current that could potentially cause damage, the regulator transitions to a current control mode. In the current control mode, the regulator supplies power with a fluctuating voltage level and a maximum current level. The regulator transitions between voltage control mode and current control mode in order to supply a maximum power level to the load without exceeding the maximum current level. The regulator is also configured to limit the power drawn from the battery by decreasing the maximum output current, potentially avoiding voltage droop. | 03-05-2015 |