Patent application number | Description | Published |
20120307838 | METHOD AND SYSTEM FOR TEMPORARY DATA UNIT STORAGE ON INFINIBAND HOST CHANNEL ADAPTOR - A method for temporary storage of data units including receiving a first data unit to store in a hardware linked list queue on a communications adapter, reading a first index value from the first data unit, determining that the first index value does match an existing index value of a first linked list, and storing the first data unit in the hardware linked list queue as a member of the first linked list. The method further includes receiving a second data unit, reading a second index value from the second data unit, determining that the second index value does not match any existing index value, allocating space in the hardware linked list queue for a second linked list, and storing the second data unit in the second linked list. | 12-06-2012 |
20120311208 | METHOD AND SYSTEM FOR PROCESSING COMMANDS ON AN INFINIBAND HOST CHANNEL ADAPTOR - A method for processing commands on a host channel adapter includes a host channel adapter receiving data from a host connected to the host channel adapter. The command includes an instruction, identification of packet data, and a length field. The host channel adapter extracts a length of the command from the length field, generates a scoreboard mask based on the length, where the scoreboard mask includes unused bits in the scoreboard preset, and sets, with each portion of the data received, a corresponding bit in a scoreboard. The host channel adapter further determines that the size of the data received for the command matches the length using the scoreboard, issues a kick on the host channel adapter when a size of the data received for the command matches the length, executes, in response to the kick, the instruction on a pipeline, and sends the packet data on a network. | 12-06-2012 |
20120311597 | METHOD AND SYSTEM FOR INFINIBAND HOST CHANNEL ADAPTOR QUALITY OF SERVICE - A method for allocating resources of a host channel adapter includes the host channel adapter identifying an underlying function referenced in the first resource allocation request received from a virtual machine manager, determining that the first resource allocation request specifies a number of physical collect buffers (PCBs) allocated to the underlying function, allocating the number of PCBs to the underlying function, determining that the first resource allocation request specifies a number of virtual collect buffers (VCBs) allocated to the underlying function, and allocating the number of VCBs to the underlying function. The host channel adapter further receives command data for a command from the single virtual machine, determines that the underlying function has in use at least the number of PCBs when the command data is received, and drops the command data in the first command based on the underlying function having in use at least the number of PCBs. | 12-06-2012 |
20140177629 | METHOD AND SYSTEM FOR INFINIBAND.RTM. HOST CHANNEL ADAPTER MULTICAST PACKET REPLICATION MECHANISM - A method for multicast replication by a host channel adapter (HCA) involving receiving a multicast packet, by a receive pipeline for processing packets of the HCA, storing, in a payload RAM within the HCA, a multicast packet payload corresponding to a data portion of the multicast packet, identifying, from a multicast header of the multicast packet, a plurality of destination underlying functions and a plurality of corresponding destination QPs to which the multicast packet is directed, wherein each destination underlying function of corresponds to a virtual machine located on a host, identifying, from the multicast header, information to be replicated for each multicast packet destination, injecting, by the HCA, a number of multicast packet descriptors corresponding to a number of the corresponding destination QPs into the receive pipeline of the HCA, and copying, from the payload RAM, the multicast packet payload to each of the corresponding destination QPs. | 06-26-2014 |
20140177633 | METHOD AND SYSTEM FOR DYNAMIC REPURPOSING OF PAYLOAD STORAGE AS A TRACE BUFFER - A method for debugging network activity involving receiving, by HCA, a packet stream comprising multiple packets, comparing a packet header of each of the packets to a trigger condition to determine whether the trigger condition has been met, after the trigger condition has been met, comparing each packet header of the packets to one or more trace filters stored in the HCA to identify matching packets, duplicating one or more portions of the matching packets and storing the duplicated portions of the matching packets in a trace buffer, where the trace buffer is located in the HCA and is dynamically repurposed from a payload RAM to the trace buffer when a corresponding port of the HCA for transmitting or receiving the packet stream is set to trace mode, and stopping the trace and copying the one or more portions of packets from the trace buffer to host memory. | 06-26-2014 |
20140181232 | DISTRIBUTED QUEUE PAIR STATE ON A HOST CHANNEL ADAPTER - A method for managing a distributed cache of a host channel adapter (HCA) that includes receiving a work request including a QP number, determining that a QP state identified by the QP number is not in the distributed cache, retrieving the QP state from main memory, and identifying a first portion and a second portion of the QP state. The method further includes storing the first portion into a first entry of a first sub-cache block associated with the first module, where the first entry is identified by a QP index number, storing the second portion into a second entry of a second sub-cache block associated with the second module, where the second entry is identified by the QP index number; and returning the QP index number of the QP state to the first module and the second module. | 06-26-2014 |
20140181241 | METHOD AND SYSTEM FOR AN ON-CHIP COMPLETION CACHE FOR OPTIMIZED COMPLETION BUILDING - A method for optimizing completion building is disclosed. The method involves receiving a work request by a host channel adapter (HCA), caching a portion of the work request in a completion cache in the HCA, wherein the cached portion of the work request includes information for building a completion for the work request, receiving, by the HCA, a response to the work request, querying the completion cache upon receiving the response to the work request to obtain the cached portion of the work request, and building the completion for the work request using the cached portion of the work request, wherein the completion informs a software application of at least a status of the work request as executed by the HCA. | 06-26-2014 |
20140181323 | Doorbell backpressure avoidance mechanism on a host channel adapter - A method for processing commands includes receiving, for multiple commands, doorbells for writing to a send queue scheduler buffer on a host channel adapter (HCA). The send queue scheduler buffer is associated with a send queue scheduler. The method further includes detecting a potential deadlock of the send queue scheduler from processing a portion of the doorbells, writing a subset of the doorbells to a doorbell overflow buffer on a host, operatively connected to the HCA, based on detecting the potential deadlock, and discarding the subset by the send queue scheduler without processing the subset of the plurality of doorbells before discarding. | 06-26-2014 |
20140181409 | METHOD AND SYSTEM FOR QUEUE DESCRIPTOR CACHE MANAGEMENT FOR A HOST CHANNEL ADAPTER - A method for managing a queue descriptor cache of a host channel adaptor (HCA) includes obtaining a queue descriptor from memory. The queue descriptor includes data describing a queue and the memory is located in a host system. The method further includes storing a copy of the queue descriptor in the queue descriptor cache of the HCA. The HCA accesses the copy of the queue descriptor to obtain the plurality of data, accesses the queue using the data, and updates the data to reflect the access to the queue. The method further includes calculating, using the data, a value corresponding to utilization of the queue, comparing the value against a threshold, fetching, if the value exceeds the threshold, a new copy of the queue descriptor from memory, and replacing the copy of the queue descriptor in the queue descriptor cache with the new copy obtained from the memory. | 06-26-2014 |
20140181454 | METHOD AND SYSTEM FOR EFFICIENT MEMORY REGION DEALLOCATION - A method for deallocation of a memory region involving transmitting, by a host channel adapter (HCA), a first invalidation command for invalidating at least one key associated with the memory region, transmitting, by the HCA, a second invalidation command for invalidating a translation lookaside buffer (TLB) entry for the memory region, invalidate the at least one key associated with the memory region, determining whether all memory access requests to the memory region have been processed by the HCA, stalling processing of the second invalidation command when outstanding memory access requests to the memory region are present, and processing the outstanding memory access requests for the memory region by the HCA before executing the second invalidation command invalidating the TLB entry for the memory region. | 06-26-2014 |
20140181823 | PROXY QUEUE PAIR FOR OFFLOADING - A method for offloading includes a host channel adapter (HCA) receiving a first work request identifying a queue pair (QP), making a first determination that the QP is a proxy QP, and offloading the first work request to a proxy central processing unit (CPU) based on the first determination and based on the first work request satisfying a filter criterion. The HCA further receives a second work request identifying the QP, processes the second work request without offloading based on the QP being a proxy QP and based on the first work request failing to satisfy the filter criterion. The HCA redirects a first completion for the first work request and a second completion for the second work request to the proxy CPU based on the first determination. The proxy CPU processes the first completion and the second completion in order. | 06-26-2014 |
20140244866 | BANDWIDTH AWARE REQUEST THROTTLING - A method for managing bandwidth of a bus connecting a peripheral device to a host system includes sending, over the bus, a first read request to the host system, incrementing a pending read counter by an amount corresponding to the requested data, receiving, in response to sending the first read request, at least a portion of the requested data from the host system, decrementing the pending read counter by an amount corresponding to the at least the portion of the requested data, and comparing the counter and a threshold to obtain a result. Based on the result, a scheme is selected for managing the bandwidth of the bus. The scheme specifies a ratio of read requests and write requests to be sent on the bus. The method further includes sending, based on the scheme, a second request that is a write request or a second read request. | 08-28-2014 |
20140244965 | METHOD AND SYSTEM FOR SIMPLIFIED ADDRESS TRANSLATION SUPPORT FOR STATIC INFINIBAND HOST CHANNEL ADAPTOR STRUCTURES - A method for optimized address pre-translation for a host channel adapter (HCA) static memory structure is disclosed. The method involves determining whether the HCA static memory structure spans a contiguous block of physical address space, when the HCA static memory structure spans the contiguous block of physical address space, requesting a translation from a guest physical address (GPA) to a machine physical address (MPA) of the HCA static memory structure, storing a received MPA corresponding to the HCA static memory structure in an address control and status register (CSR) associated with the HCA static memory structure, marking the received MPA stored in the address CSR as a pre-translated address, and using the pre-translated MPA stored in the address CSR when a request to access the static memory structure is received. | 08-28-2014 |
20140245092 | CAM BIT ERROR RECOVERY - A method for content addressable memory (CAM) error recovery that includes detecting an error in an entry of a CAM, identifying an address of the entry in the CAM, copying data from the address in the backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM, clearing a results (first in first out) FIFO structure based on detecting the error, performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result, and storing the revised result in the results FIFO structure. | 08-28-2014 |
Patent application number | Description | Published |
20130100664 | INTERNAL COLLECTING REFLECTOR OPTICS FOR LEDS - An optical system is disclosed that uses an LED light source. The light output is coupled to an optic element formed from a material with a high refractive index. The coupling of the light to the high index material significantly reduces the cone angle of the light. The system is very efficient in that nearly all the light generated by the LED is directed to the intended subject. | 04-25-2013 |
20140071329 | RECONFIGURABLE OPTICAL DEVICE USING A TOTAL INTERNAL REFLECTION (TIR) OPTICAL SWITCH - An optical device having a total internal reflection (TIR) switch is able to switch to form two different optical imaging paths. Each optical imaging path has different optical characteristics that causes a detector to capture different imagery depending upon which optical imaging path is used. The TIR switch is switchable between a TIR state and a transmission state to control which optical imaging path is used by the device for imaging. | 03-13-2014 |
20140083025 | ANCHORING SYSTEM WITH POST ANGULAR ADJUSTMENT - A post securing system that secures a post in the ground, while allowing for a full range of vertical adjustment via a coupling assembly that includes an articulating ball joint element that is connected to a post support element secured within two clamp assemblies. The clamp assemblies each include an anchor assembly which, when assembled, secures at least three stake elements at a predetermined angle. The post securing kit includes both the coupling assembly and the anchor assembly to allow securing a post into a non-horizontal ground, while maintaining the desired vertical alignment of the post held therewithin. | 03-27-2014 |
20140250820 | TRUSS SYSTEM WITH INTEGRAL CHANNELS - A truss system designed to simplify the addition of lights, audio equipment, and other stage-related equipment through the use of essentially circular strut channel members. The system is designed to enclose such equipment, be lightweight, and facilitate easy set-up and take-down of truss assemblies. The lightweight truss system includes an open-sided structure with rigid ends, and a strut channel system that facilitates the installation of lights, audio equipment, and other stage-related devices. | 09-11-2014 |
20140262456 | HIGH ASPECT RATIO TRACES, CIRCUITS, AND METHODS FOR MANUFACTURING AND USING THE SAME - High aspect ratio trace circuits and methods of manufacture and use are provided herein. A method may include obtaining a substrate, the substrate having a reservoir for receiving a conductive ink and a plurality of trace voids that are arranged in a pattern, the plurality of trace voids each having a path of fluid connection to the reservoir, filling the reservoir with a conductive ink, placing a cover film over the plurality of trace voids, allowing the conductive ink to fill the plurality of trace voids via capillary action to create a plurality of conductive traces, and allowing the conductive ink in the plurality of conductive traces to dry. | 09-18-2014 |
20150109780 | LIGHTING ASSEMBLY HAVING n-FOLD ROTATIONAL SYMMETRY - A lighting assembly includes an LED light source assembly and a unitary light-transmissive solid reflector optical element. The reflector optical element has a light output surface and n light-transmissive solid optical sub-elements having n-fold rotationally symmetrical about a central axis. Boundaries between adjacent optical sub-elements extend radially outward from the central axis. Each optical sub-element has a reflective surface positioned opposite the light output surface on the optical sub-element and shaped to create an internal reflection effect. The LED light source assembly has an LED light source for each optical sub-element. The LED light sources are positioned along an outline near the light output surface to direct light from each LED light source towards the reflective surface of the respective optical sub-element such that the light is reflected by the reflective surface to form an output light that exits the reflector optical element through the light output surface. | 04-23-2015 |