Patent application number | Description | Published |
20090085062 | METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region. | 04-02-2009 |
20090230478 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMACE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 09-17-2009 |
20100065888 | High mobility tri-gate devices and methods of fabrication - A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees. | 03-18-2010 |
20100079924 | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby - A method of patterning a metal ( | 04-01-2010 |
20100155848 | Trigate static random-access memory with independent source and drain engineering, and devices made therefrom - A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (R | 06-24-2010 |
20100155887 | Common plate capacitor array connections, and processes of making same - A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height. | 06-24-2010 |
20100285279 | METHODS OF FORMING NANODOTS USING SPACER PATTERNING TECHNIQUES AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots. | 11-11-2010 |
20110018063 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMANCE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 01-27-2011 |
20110062512 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 03-17-2011 |
20110134583 | METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY - A method of patterning a metal ( | 06-09-2011 |
20120012934 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 01-19-2012 |
20120292709 | TRIGATE STATIC RANDOM-ACCESS MEMORY WITH INDEPENDENT SOURCE AND DRAIN ENGINEERING, AND DEVICES MADE THEREFROM - A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (R | 11-22-2012 |
20130234290 | METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY - A method of patterning a metal ( | 09-12-2013 |
20140084398 | PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER - Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer. | 03-27-2014 |
20140097495 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMANCE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 04-10-2014 |
20140291663 | HIGH STABILITY SPINTRONIC MEMORY - An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein. | 10-02-2014 |
20140349415 | PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER - Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer. | 11-27-2014 |