Patent application number | Description | Published |
20100187879 | JUVENILE VEHICLE SEAT WITH HEADREST-HEIGHT CONTROLLER - According to the present disclosure, a juvenile vehicle seat includes a base providing a seat bottom, a backrest extending upwardly from the base, and a movable headrest. The headrest is mounted for up-and-down movement on the backrest. The juvenile vehicle seat also includes a headrest-height controller configured to control the height of the movable headrest relative to the backrest. | 07-29-2010 |
20100187880 | JUVENILE VEHICLE SEAT WITH LAP BELT LOCK-OFF MECHANISM - A seat support for a juvenile restraint adapted to receive a juvenile seat. The seat support includes an anchor belt retainer for anchoring a seat-base anchor belt to the seat support and for anchoring a vehicle anchor belt to the seat support. | 07-29-2010 |
20100201170 | HARNESS SYSTEM FOR JUVENILE VEHICLE SEAT - A child restraint having a juvenile vehicle seat, a harness for securing a juvenile to the juvenile vehicle seat, and a harness-positioning system for positioning the harness in an open juvenile-receiving position. | 08-12-2010 |
20100253120 | JUVENILE VEHICLE SEAT WITH SEAT-BACK CHANNEL COVER - A child restraint includes a juvenile vehicle seat and a movable headrest mounted on the seat. The seat includes a base, a back, and a child-restraint harness coupled to the base and to the movable headrest. The child-restraint harness includes shoulder belts arranged to pass through openings formed in the seat back and the movable headrest. | 10-07-2010 |
Patent application number | Description | Published |
20120120560 | METAL-ENCAPSULATED, POLYPHASE, GAS-INSULATED BUSBAR SWITCH DISCONNECTOR AND EARTHING SWITCH - Exemplary embodiments are directed to a metal-encapsulated, polyphase busbar switch disconnector and earthing switch, including a housing which, on each of opposite sides has three flanges that lie on a plane. Each flange being connected to one busbar and, on a third side, a flange is connected to a circuit breaker. The circuit breaker having conductor elements arranged in an interior of the housing. First conductor elements are connected to the busbars, and second conductor elements are connected to circuit breaker poles. The second conductor elements are aligned at right angles to the first conductor elements, which connect the busbars to one another, such that the first conductor elements are substantially U-shaped and are passed around the second conductor elements. A switch disconnector and earthing switch contact arrangement is provided between an inner housing wall and the first and second conductor elements. | 05-17-2012 |
20140174895 | CONTACT ARRANGEMENT FOR HIGH VOLTAGE SWITCHGEAR WITH CONTACT ARRANGEMENT - A contact arrangement has a symmetry axis (z) and includes at least a first elongated contact and at least a second elongated contact. At least one of the contacts is movable linearly along the axis (z) relative to the other contact and contacts it electrically and mechanically at a front face of each contact. The first and/or the second contact is at least partially hollow, thereby forming a hollow space in its interior. A diameter, with regard to the axis (z), of the hollow space of the first and/or the second contact varies along at least a section of the hollow space and the hollow space has an opening on the front face of the first and/or the second contact. | 06-26-2014 |
20150034599 | HIGH VOLTAGE INTERRUPTER UNIT WITH IMPROVED MECHANICAL ENDURANCE - A high voltage interrupter unit includes a switching chamber within which at least two electric contact elements of a contact system are arranged to be moved relative to one another. The contact system includes at least one mechanical element which is at least in part not in fixed mechanical connection with either of the two contact elements. In order to increase the mechanical endurance of the contact system, the at least one mechanical element is sheathed at least in part in a layer of a synthetic, abrasion resistant material. | 02-05-2015 |
Patent application number | Description | Published |
20130155788 | DDR 2D VREF TRAINING - A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain. | 06-20-2013 |
20130159615 | DDR RECEIVER ENABLE CYCLE TRAINING - A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed. | 06-20-2013 |
20150078104 | DDR 2D VREF TRAINING - A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain. | 03-19-2015 |
20150089168 | NESTED CHANNEL ADDRESS INTERLEAVING - A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits. | 03-26-2015 |
20150100723 | DATA PROCESSOR WITH MEMORY CONTROLLER FOR HIGH RELIABILITY OPERATION AND METHOD - A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (t | 04-09-2015 |
20150221358 | MEMORY AND MEMORY CONTROLLER FOR HIGH RELIABILITY OPERATION AND METHOD - In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window. | 08-06-2015 |