Patent application number | Description | Published |
20090013209 | APPARATUS FOR CONNECTION MANAGEMENT AND THE METHOD THEREFOR - An apparatus and method for scheduling data distributions to or results information from, or collectively, “jobs” a plurality of data processing systems via a network. A connection to a target system is created. For each distribution, a session, which is an independent thread, is allocated from one of a plurality of pool of sessions and launched to effect execution of the job. Each pool corresponds to a predetermined priority level, and the session is allocated from the pool having the same priority level as the priority level of the job being scheduled. A connection supports a multiplicity of independent threads. In the event of an error, the session is released, and the scheduling of the aborted job is retried after a predetermined retry interval expires. After expiry of the retry interval, a callback method is invoked when the target system on which the scheduled job is executed becomes accessible. | 01-08-2009 |
20120297087 | Method And Apparatus For Message Distribution In A Device Management System - A method and apparatus for managing CPE devices. In managing a CPE, an ACS must first establish a communication session with the CPE. In accordance with the present invention, the connection request formed by the ACS and containing proxy information is transmitted to a primary blast box. The primary blast box, which includes a blast box registry, forwards the connection request to a plurality of secondary blast boxes, each secondary blast box being associated with a respective CGN private network of the communications network. The secondary blast boxes in turn removes the proxy information and forwards the connection request to one or more CPEs in the private network encompassed by the corresponding CGN. Authentication information sent with the proxy information uniquely permits authentication of the connection request in the target CPE. When authentication occurs, the CPE initiates a communication session with the ACS so that the desired management function may be executed. | 11-22-2012 |
20130097322 | SCALABLE DISTRIBUTED MULTICLUSTER DEVICE MANAGEMENT SERVER ARCHITECTURE AND METHOD OF OPERATION THEREOF - A server architecture for, and method of, managing devices. In one embodiment, the server architecture includes: (1) a plurality of manager clusters and (2) a dispatcher cluster coupled to the plurality of manager clusters and configured to: (2a) receive an initial contact from a device, (2b) assign the device to one manager cluster of the plurality of manager clusters, the one manager cluster becoming a home cluster for the device, (2c) cause data regarding the device to be transferred to the home cluster and (2d) cause the device thereafter to communicate directly with, and be managed by, the home cluster. | 04-18-2013 |
20130268578 | Method And Apparatus For Facilitating Communications With A Managed Client Device - A method and apparatus for facilitating communications between a managing server and a client device. The managing server may be an ACS operable to configure a CPE to received connection request from an external server, which thereby brokers initiation of a communication session between the CPE and the ACS. The external server also preferably determines what type of connection request to use and provides configuration parameters to the ACS. | 10-10-2013 |
Patent application number | Description | Published |
20100153053 | Stream Based Stimulus Definition and Delivery via Interworking - An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor. | 06-17-2010 |
20110107146 | Trace Reconstruction for Silicon Validation of Asynchronous Systems-on-Chip - A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions. | 05-05-2011 |
20140072028 | VIDEO AND IMAGE COMPRESSION BASED ON POSITION OF THE IMAGE GENERATING DEVICE - An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device. | 03-13-2014 |
20150052174 | ADAPTIVE BINNING OF VERIFICATION DATA - Exemplary embodiments for adaptive binning of verification data comprise defining in a memory by at least one processor a data organization tree having a self-modifying bin structure that automatically modifies in response to input raw verification data; responsive to receiving a stream of verification data, identifying patterns in the verification data based on business knowledge of subcategories of the data; and using the data organization tree to automatically bin together the verification data that match the identified patterns to provide an aggregate view of the verification data. | 02-19-2015 |
Patent application number | Description | Published |
20130236568 | PHOSPHAPLATINS HAVING ANTI-ANGIOGENIC, ANTI-METASTATIC, AND PRO-APOPTOTIC PROPERTIES AND USES THEREOF - Provided are compositions and uses thereof in methods of inhibiting angiogenesis, metastasis, or both, wherein said compositions comprise phosphaplatins such as pyrodach-4. In some embodiments, provided are compositions and uses thereof in methods of treating sensitive and resistant cancers. | 09-12-2013 |
20130237503 | PHOSPHAPLATINS AND THEIR USE IN THE TREATMENT OF CANCERS RESISTANT TO CISPLATIN AND CARBOPLATIN - The present invention provides pharmaceutical compositions comprising phosphaplatins, stable isolated monomeric phosphato complexes of platinum (II) and (IV). In some embodiments, such compositions may be useful for treating cancers, including cisplatin- and carboplatin-resistant cancers. The provided phosphaplatin complexes do not readily undergo hydrolysis and are quite soluble and stable in aqueous solutions. Moreover, these complexes—unlike cisplatin, carboplatin, and related platinum-based agents—do not bind DNA. Rather, data suggests that phosphaplatins trigger overexpression of fas and fas-related transcription factors and some proapoptotic genes such as Bak and Bax. Nevertheless, the complexes exhibit tremendous cytotoxicity towards cancer cells. Thus, the present invention provides novel platinum agents that have a different molecular target than those in the art. | 09-12-2013 |
20140243293 | PHOSPHAPLATINS AS NEUROPROTECTIVE AGENTS - The present disclosure provides for compositions for the treatment of neurodegenerative diseases comprising one or more isolated phosphate complexes of platinum and methods of uses thereof for treating neurodegenerative diseases including amyotrophic lateral sclerosis, Alzheimer's disease, stroke, epilepsy, Parkinsons, Huntington's disease and diabetes associated peripheral neuropathy The present disclosure is also directed towards an anti-angiogenic composition useful for inhibiting angiogenesis related to age-related macular degeneration, diabetic retinopathy and tumor-associated angiogenesis. An embodiment of the present disclosure is also directed towards a method for modulating the expression of Pigment Epithelial Derived Factor (PEDF) gene in an individual in need thereof. The present disclosure also provides for a method of reducing neurotoxicity associated with the administration of a cancer therapy in a subject in need thereof comprising administering to the individual in need thereof a therapeutically effective amount of at least one or more isolated monomeric phosphate complexes of platinum described herein. | 08-28-2014 |
Patent application number | Description | Published |
20080216025 | Tunneling as a Boundary Congestion Relief Mechanism - Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node population. | 09-04-2008 |
20080216038 | Timing Driven Force Directed Placement Flow - Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof. | 09-04-2008 |
20080216039 | Node Spreading via Artificial Density Enhancement to Reduce Routing Congestion - Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. | 09-04-2008 |
20080216040 | Incremental Relative Slack Timing Force Model - Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. | 09-04-2008 |
20090254874 | METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING - Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof. | 10-08-2009 |