Patent application number | Description | Published |
20090133003 | COMMAND LANGUAGE FOR MEMORY TESTING - A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing. | 05-21-2009 |
20090282303 | BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM - An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist. | 11-12-2009 |
20090316507 | Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories - The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal. | 12-24-2009 |
20100017622 | High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks - The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device. | 01-21-2010 |
20100191935 | Architecture and implementation method of programmable arithmetic controller for cryptographic applications - An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography. | 07-29-2010 |
Patent application number | Description | Published |
20120076298 | UNIFIED ARCHITECTURE FOR CRYPTO FUNCTIONAL UNITS - In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks. | 03-29-2012 |
20120226731 | LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER - A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field. | 09-06-2012 |
20120324319 | HIGH THROUGHPUT FRAME CHECK SEQUENCE MODULE ARCHITECTURE - Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products. | 12-20-2012 |
20130283114 | Systems and Methods for Locating and Correcting Decoder Mis-Corrections - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit. | 10-24-2013 |
20130346824 | DYNAMICALLY CONTROLLING THE NUMBER OF LOCAL ITERATIONS IN AN ITERATIVE DECODER - An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding. | 12-26-2013 |
20140068367 | LDPC Decoder Trapping Set Identification - The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder. | 03-06-2014 |
20140075264 | CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING - A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword. | 03-13-2014 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 06-12-2014 |
20140168811 | Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling - A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome. | 06-19-2014 |
20140281284 | MULTI-READ PORT MEMORY - A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request. | 09-18-2014 |
20140289582 | Systems and Methods for Reduced Constraint Code Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 09-25-2014 |
20140325303 | Systems and Methods for Protected Data Encoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for encoding data sets. | 10-30-2014 |
Patent application number | Description | Published |
20150109296 | GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR UPDATING VOXEL REPRESENTATION OF A SCENE - A graphics processing subsystem and method for updating a voxel representation of a scene. One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a voxel representation of a scene having first and second regions to be updated, and (2) a graphics processing unit (GPU) operable to: (2a) unify the first and second regions into a bounding region if a volume thereof does not exceed summed volumes of the first and second regions by more than a tolerance, and (2b) generate voxels for the bounding region and cause the voxels to be stored in the voxel representation. | 04-23-2015 |
20150109297 | GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR COMPUTING A THREE-DIMENSIONAL CLIPMAP - A graphics processing subsystem and method for computing a 3D clipmap. One embodiment of the subsystem includes: (1) a renderer operable to render a primitive surface representable by a 3D clipmap, (2) a geometry shader (GS) configured to select respective major-plane viewports for a plurality of clipmap levels, the major-plane viewports being sized to represent full spatial extents of the 3D clipmap relative to a render target (RT) for the plurality of clipmap levels, (3) a rasterizer configured to employ the respective major-plane viewports and the RT to rasterize a projection of the primitive surface onto a major plane corresponding to the respective major-plane viewports into pixels representing fragments of the primitive surface for each of the plurality of clipmap levels, and (4) a plurality of pixel shader (PS) instances configured to transform the fragments into respective voxels in the plurality of clipmap levels, thereby voxelizing the primitive surface. | 04-23-2015 |
20150109298 | COMPUTING SYSTEM AND METHOD FOR REPRESENTING VOLUMETRIC DATA FOR A SCENE - A computing system and method for representing volumetric data for a scene. One embodiment of the computing system includes: (1) a memory configured to store a three-dimensional (3D) clipmap data structure having at least one clip level and at least one mip level, and (2) a processor configured to generate voxelized data for a scene and cause the voxelized data to be stored in the 3D clipmap data structure. | 04-23-2015 |
20150109300 | SYSTEM AND METHOD FOR COMPUTING REDUCED-RESOLUTION INDIRECT ILLUMINATION USING INTERPOLATED DIRECTIONAL INCOMING RADIANCE - A system for, and method of, computing reduced-resolution indirect illumination using interpolated directional incoming radiance and a graphics processing subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cone tracing shader executable in a graphics processing unit to compute directional incoming radiance cones for sparse pixels and project the directional incoming radiance cones on a basis and (2) an interpolation shader executable in the graphics processing unit to compute outgoing radiance values for untraced pixels based on directional incoming radiance values for neighboring ones of the sparse pixels. | 04-23-2015 |