Patent application number | Description | Published |
20090101983 | Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits - Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays. | 04-23-2009 |
20090125865 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught. | 05-14-2009 |
20090300567 | DESIGN LAYOUT OF PRINTABLE ASSIST FEATURES TO AID TRANSISTOR CONTROL - Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p | 12-03-2009 |
20100031216 | METHOD FOR LAYOUT OF RANDOM VIA ARRAYS IN THE PRESENCE OF STRONG PITCH RESTRICTIONS - Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first intersecting point of a grid. The placed first feature can define a local grid area. The local grid area can further include a plurality of local intersecting points having an outer perimeter spaced from any outermost local intersecting point in a spacing ranging from a length of a grid side to a length of a grid diagonal of a grid unit. A second feature can either be restrictively placed on any local intersecting point of the local grid area, or be randomly placed on any location outside the outer perimeter of the local grid area. | 02-04-2010 |
20100167484 | Gate line edge roughness reduction by using 2P/2E process together with high temperature bake - A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process. | 07-01-2010 |
20100167513 | DUAL ALIGNMENT STRATEGY FOR OPTIMIZING CONTACT LAYER ALIGNMENT - An improved method for optimizing layer registration during lithography in the fabrication of a semiconductor device is disclosed. In one example, the method comprises optimizing contact layer registration of an SRAM device having a plurality of transistors having active and gate region features extending generally along a channel length (X) direction and a channel width (Y) direction, respectively. The method comprises aligning a contact layer to a gate layer in the channel length direction (X), using gate layer overlay marks to control the alignment of the contact layer in the channel length direction (X) of the semiconductor device. The method further includes aligning the contact layer to an active layer in the channel width direction (Y), using active layer overlay marks to control the alignment of the contact layer in the channel width direction (Y) of the semiconductor device. | 07-01-2010 |
20120107729 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 05-03-2012 |
20120131522 | METHOD FOR GENERATING ULTRA-SHORT-RUN-LENGTH DUMMY POLY FEATURES - A method and apparatus for designing a lithography mask set which provides polygon features of a desired size at advanced technology nodes, for example, using live features and dummy features. A dummy feature can be formed within a confined space by specifying an allowable dummy feature length even though the feature length may result in contact between the dummy feature and the live feature. After specifying the dummy feature length, a pattern generation (PG) extract can be performed to pull back the dummy feature away from the live feature by an allowable distance. The PG exact process can result in a shorter dummy feature which has a length which is shorter than can be specified directly by design rules, but which passes rule checking. | 05-24-2012 |
20120148942 | DIAGONAL INTERCONNECT FOR IMPROVED PROCESS MARGIN WITH OFF-AXIS ILLUMINATION - Mask or reticle methods and structures having pattern feature segments formed at oblique angles to each other. When illuminated using off-axis illumination techniques, a mask or reticle according to the present teachings can result in a more accurately reproduced feature within a photosensitive layer. | 06-14-2012 |
20120223439 | TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA - An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements. | 09-06-2012 |
20120225550 | HYBRID PITCH-SPLIT PATTERN-SPLIT LITHOGRAPHY PROCESS - An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks. | 09-06-2012 |
20120225551 | PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAPHY PROCESS - An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern. | 09-06-2012 |
20120225552 | TWO-TRACK CROSS-CONNECTS IN DOUBLE-PATTERNED METAL LAYERS USING A FORBIDDEN ZONE - An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines. | 09-06-2012 |
20120227015 | PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMINATION CONDITIONS FOR LITHOGRAPHY PROCESS - A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration. | 09-06-2012 |
20120331425 | MANUFACTURABILITY ENHANCEMENTS FOR GATE PATTERNING PROCESS USING POLYSILICON SUB LAYER - A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set. | 12-27-2012 |
20130069081 | Layout Method To Minimize Context Effects and Die Area - An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor. | 03-21-2013 |
20130069168 | SRAM LAYOUT FOR DOUBLE PATTERNING - An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns. | 03-21-2013 |
20130069170 | ILLUMINATION AND DESIGN RULE METHOD FOR DOUBLE PATTERNED SLOTTED CONTACTS - An integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width. A method for forming an integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width. | 03-21-2013 |
20130069244 | RECTANGULAR VIA FOR ENSURING VIA YIELD IN THE ABSENCE OF VIA REDUNDANCY - A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication. | 03-21-2013 |
20130072020 | Method For Ensuring DPT Compliance for Auto-Routed Via Layers - A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set. | 03-21-2013 |
20130074028 | METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS - A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set. | 03-21-2013 |
20130074029 | Method To Ensure Double Patterning Technology Compliance In Standard Cells - An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells. | 03-21-2013 |
20130244144 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 09-19-2013 |
20130246983 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 09-19-2013 |
20140035160 | TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA - An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements. | 02-06-2014 |
20140101622 | PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMINATION CONDITIONS FOR LITHOGRAPHY PROCESS - A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration. | 04-10-2014 |