Patent application number | Description | Published |
20130292767 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE AND METHOD - A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate. | 11-07-2013 |
20130320494 | METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS - A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction. | 12-05-2013 |
20140036578 | SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT - Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node. | 02-06-2014 |
20140092523 | BONE FRAME, LOW RESISTANCE VIA COUPLED METAL OXIDE-METAL (MOM) ORTHOGONAL FINGER CAPACITOR - An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame. | 04-03-2014 |
20140138793 | CAPACITOR USING MIDDLE OF LINE (MOL) CONDUCTIVE LAYERS - A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL, conductive layer on the insulator layer as a second plate of the MIM capacitor. | 05-22-2014 |
20140197519 | MIM CAPACITOR AND MIM CAPACITOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique. | 07-17-2014 |
20140197520 | RESISTOR AND RESISTOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. | 07-17-2014 |
20140203401 | METAL-ON-METAL (MOM) CAPACITORS HAVING LATERALLY DISPLACED LAYERS, AND RELATED SYSTEMS AND METHODS - Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor. | 07-24-2014 |
20140203404 | SPIRAL METAL-ON-METAL (SMOM) CAPACITORS, AND RELATED SYSTEMS AND METHODS - Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability. | 07-24-2014 |
20140211546 | STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS - Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance. | 07-31-2014 |
20140219016 | SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL - A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate. | 08-07-2014 |
20140231957 | COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR - A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s). | 08-21-2014 |
20140252543 | METAL-OXIDE-METAL (MOM) CAPACITOR WITH ENHANCED CAPACITANCE - A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure. | 09-11-2014 |
20140264485 | FIN-TYPE SEMICONDUCTOR DEVICE - An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration. | 09-18-2014 |
20140264610 | METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS - Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa. | 09-18-2014 |
20150028452 | COMPLEMENTARY BACK END OF LINE (BEOL) CAPACITOR - A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s). | 01-29-2015 |
20150035039 | LOGIC FINFET HIGH-K/CONDUCTIVE GATE EMBEDDED MULTIPLE TIME PROGRAMMABLE FLASH MEMORY - A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film. | 02-05-2015 |
20150036437 | FLASH MEMORY CELL WITH CAPACITIVE COUPLING BETWEEN A METAL FLOATING GATE AND A METAL CONTROL GATE - An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line. | 02-05-2015 |
20150050785 | METHOD OF FORMING A COMPLEMENTARY METAL-OXIDESEMICONDUCTOR (CMOS) DEVICE - A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer. | 02-19-2015 |
20150069458 | VERTICAL TUNNEL FIELD EFFECT TRANSISTOR - A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall. | 03-12-2015 |