Bhowmik
Amit Bhowmik, Navi Mumbai IN
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20150051940 | SYSTEMS AND METHODS FOR SUPPLY CHAIN DESIGN AND ANALYSIS - Systems and methods for supply chain design and analysis to optimize costs associated with a supply chain are described. According to an embodiment, the supply chain management system comprises a data extraction module, an analysis module, and a presentation module coupled to a processor. The data extraction module obtains supply chain data from one or more data sources. The analysis module analyzes a plurality of parameters and at least one future state map to ascertain at least one business scenario. Further, the analysis module identifies flow constraints in the at least one business scenario based on a flow analysis. Further, the analysis module selects decision parameters from amongst the plurality of parameters based on the flow constraints and a simulation feedback. Further, the analysis module simulates at least one experimental design based on the decision parameters. Furthermore, the presentation module generates, a plurality of maps based on visual analytics. | 02-19-2015 |
Ayan Bhowmik, Cambridge GB
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20130121823 | CHROMIUM ALLOY - A hypereutectic chromium alloy consisting of 9 to 12 at % tantalum, 4 to 15 at % silicon, 0 to 7 at % molybdenum, 0 to 7 at % aluminium, 0 to 7 at % titanium, 0 to 5 at % rhenium, 0 to 2 at % silver, 0 to 2 at % hafnium, 0 to 2 at % lanthanum, 0 to 2 at % cerium, 0 to 2 at % yttrium and the balance chromium and incidental impurities. The hypereutectic chromium alloy has good oxidation resistance and good fracture toughness. The chromium alloy may be used to make gas turbine engine turbine blades, turbine vanes, turbine seals, combustion chamber tiles, exhaust nozzle segments or steam turbine components. | 05-16-2013 |
Dipal Ranjan Bhowmik, Midnapore IN
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20090048335 | PROCESS FOR PREPARING SIMVASTATIN - Preparation of simvastatin. | 02-19-2009 |
Prasenjit Bhowmik, Tripura IN
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20120319789 | RELAXATION OSCILLATOR CIRCUIT WITH REDUCED SENSITIVITY OF OSCILLATION FREQUENCY TO COMPARATOR DELAY VARIATION - A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor. | 12-20-2012 |
Prasenjit Bhowmik, Agartala IN
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20090295609 | SYSTEM AND METHOD FOR REDUCING POWER DISSIPATION IN AN ANALOG TO DIGITAL CONVERTER - A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs. | 12-03-2009 |
Prasenjit Bhowmik, Bangalore IN
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20100164606 | DC BIASING CIRCUIT FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR - A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes. | 07-01-2010 |
20100164611 | LEAKAGE INDEPENDENT VRY LOW BANDWIDTH CURRENT FILTER - A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit. | 07-01-2010 |
20140145768 | CORRECTING FOR OFFSET-ERRORS IN A PLL/DLL - The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for. | 05-29-2014 |
20150042386 | HIGHLY ACCURATE POWER-ON RESET CIRCUIT WITH LEAST DELAY - A power-on reset (POR) circuit for generating a POR signal includes a current source to generate an input current. The input current is a supply voltage dependent current. The POR circuit includes a first diode operable to receive the input current to output a first voltage signal. The first diode is electrically connected in series with a resistor. Further, the POR circuit includes a second diode operable to receive the input current to output a second voltage signal. Further, the POR circuit includes a comparator operable to receive the first voltage signal and the second voltage signal to generate the POR signal at a predefined trip point. The predefined trip point is a point at which the first voltage signal equals the second voltage signal. Furthermore, the POR circuit includes a temperature compensation circuit to compensate for the variation of the predefined trip point. | 02-12-2015 |
Sudip Bhowmik, Bangalore IN
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20100011026 | METHOD AND SYSTEM FOR DYNAMICALLY COLLECTING DATA FOR CHECKPOINT TUNING AND REDUCE RECOVERY TIME - A system and method for checkpoint tuning in a computer environment comprising a processor coupled to a statistical database and at least one database or table manager and data log files. The data log files store data relating to the operations of the database or table manager. The processor executes a module that captures data comprising the number of operations, the time taken by the checkpoint process, folded journal entries, long running transactions, and the ratio of WRITE:READ operations. The processor then stores the captured data and processes the collected data, generating statistics therefrom. The statistical data is stored in the statistical database. The system selects checkpoint intervals based on the data statistics; and implements the checkpoint intervals. | 01-14-2010 |
Sumanta Kumar Bhowmik, New Delhi IN
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20130318031 | DISTRIBUTED PROCESSING OF STREAMING DATA RECORDS - Representative embodiments of a distributed processing method of facilitating interactive analytics of streaming data records by receiving the data records at a plurality of distributed computational nodes, establishing and storing dimensions corresponding to attributes of the data records, parsing the streaming data records to identify matches to at least one of the dimensions and based thereon, reducing the number of data records to create a targeted subset of the data, re-distributing the targeted subsets of the streaming data records among the distributed computational nodes in accordance with the dimensions stored on the nodes, updating a database storing measures of the dimensions in accordance with the targeted subsets of the streaming data records, and using the database to respond to a query based on measures associated with one or more of the dimensions. | 11-28-2013 |
20130318034 | DISTRIBUTED PROCESSING OF STREAMING DATA RECORDS - Representative embodiments of a distributed processing method of facilitating interactive analytics of streaming data records by receiving the data records at a plurality of distributed computational nodes, establishing and storing dimensions corresponding to attributes of the data records, parsing the streaming data records to identify matches to at least one of the dimensions and based thereon, reducing the number of data records to create a targeted subset of the data, re-distributing the targeted subsets of the streaming data records among the distributed computational nodes in accordance with the dimensions stored on the nodes, updating a database storing measures of the dimensions in accordance with the targeted subsets of the streaming data records, and using the database to respond to a query based on measures associated with one or more of the dimensions. | 11-28-2013 |